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ITLE 361 2017 IMAPS Part 1: Xilinx HMB Integration Challenges and More

By Dr. Phil Garrou, Contributing Editor

Let’s start looking at some of the key presentations at IMAPS 2017.


Gandhi of Xilinx gave an interesting presentation on “2.5D FPGA-HBM Integration Challenges.”

Heterogeneous integration of HBM (high bandwith memory stacks) with ASIC, GPU, CPU and FPGA is real and progressing quickly. Xilinx is the frst company to attempt HM integration with partitioned FPGAs in a 2.5D format.

Xilinx 1Xilinx recently announced HBM enabled 16nm Ultrascale FPGAs which are shown below. They are built using 3rd gen CoWoS technology jointly developed by Xilinx and TSMC. The claim is that these heterogeneously integrated packages are delivering 10X the bandwidth per HBM stack and 4X lower power than DDR-4 . These packages are 55 x 55mm2.


Interposer Design – µbump pitch on the memory stacks are set by JEDEC standards. There is no std for µbump pitch on FPGAs. For ease of interposer routing, pitches across the two die need to match so that an integer number of inter die signal lines can be routed in a uniform fashion between a pair of micro bumps. This is also required from a signal timing point of view.

Package Design and Process –

xilinx 2HBM-FPGA integration for the current 16nm product required changes to bump structure and lid type. The packages moved from eutectic solder bumps to copper pillar bumps with lead free solder and a change from a copper lid to a stainless steel stiffener ring was also required. This is shown in fig below. Precise control of bare die parallelism and flatness is required to enable heat sink attachment. In the shown figure, modeling shows that co-planarity is reduced by wider ring width and/or thicker stiffener ring. They were also required to change the BGA substrate to a lower CTE core to lower the co-planarity.

Challenges in bump assembly

Addition of the HBM stacks results in open area around the HBM stacks in the layout as seen in the above pic. This results in higher warpage. Bump size and underfill type must be optimized.

ETRI (Electronics and Telecom Research Institute) Korea

ETRI has examined the “Development and Stacking Process for 3D TSV Structures using Laser.”

As part of their 3D studies they have compared bonding results between using TC (thermocompression) and laser. The bonding procedure is shown below.


The max temp of the compression bonding was 240 °C for 200 sec at a force of 1 Newton. At a laser power of 200W the max temp reached was 260 °C at a process time of 10 sec.

They concluded that there was no difference in the solder joint morphology and the electrical resistances of bonded daisy chains for both assembly technologies was the same.


Kobus presented a “Alternative Deposition Solution for Cost Reduction of TSV Integration.” Use of TSV requires isolation, barrier and copper seed deposition into the etched vias. For low AR TSV one uses PECVD and PVD techniques for the depositions. For high AR vias ALD is sometimes required. PECVD offers the highest dep rate but poor conformality. ALD results in near 100% conformality irregardless of AR, but the thickness is limited and he dep time is very slow.

FAST (Fast Atomic Sequential Technology) combines CVD and ALD to reportedly rapidly give thick, conformal depositions.

Oxide liner dep from TEOS is compared below.

Kobus 1

Electrical properties of the deposition are reportedly enhanced with 150 °C deposition resulting in BV or 9MV/cm.

TiN barrier layer is from TDEAT (tetrakisdiethylamidotitanium) and copper seed from Cupraselect™. Copper seed dep comparing FAST with PVD are shown below. They report that the field thickness (on top), resulting from copper deposition to get 200nm of copper at the bottom of a 10:1 AR via, is reduced by 2X which effects the subsequent CMP time to remove it.

kobus 2

Claims of a 24% reduction on TSV processing cost are claimed.

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