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Archive for September, 2017

IFTLE 351 ASE Tech Forum Part 3: Plasma Dicing, 2.5/3D Options

Monday, September 11th, 2017

By Dr. Phil Garrou, Contributing Editor

Several of you have asked how Hannah, Madeline and family have survived the floods down in Houston. Thanks for your concern. Luckily, the old time Texans built Rice University on high ground and my son bought in a neighborhood near there. However, that doesn’t mean they didn’t see water. The pic below shows Maddie standing on the sidewalk outside their house knee deep in water, but, as you can see to the right, it was nothing compared to other parts of the city!

madeline

 

PLASMA DICING

Finishing off our look at the ASE Tech Forum, Plasma-therm (working with ON Semi and DISCO) examined Plasma die singulation. One would look to plasma dicing to avoid the damage caused by mechanical blade dicing or the HAZ caused by Laser dicing which requires as larger than normal street to act as a keep out zone. Stress is also reduced by plasma dicing as is shown in the figure below. It is also clear that plasma dicing can result in more die per wafer due to the smaller required street/kerf.

plasmatherm 1

 

However, plasma dicing cannot etch through metal so any features in the streets (such as test structures) must be dealt with.

One solution is to isolate the test structures and process control monitors and etch around the die as shown in the fig below.

plasma-therm 2

In terms of market adoption of plasma dicing, they offered the following slide showing us what was qualified in production and what was in development.

plasmatherm 2

2.5 / 3D Technology Choices

ASE’s Chris Zinck in his examination of 3D packaging presented an interesting slide on 2.5/3D options plotting technology solutions vs substrate L/S capability. It is shown below. In their view what is evolving is a technology choice based on required density with std FC and PoP at > 10um; fan out using advanced laminate silicon-less RDL solutions between 10um and 1um and silicon interposers at less that 1 um. IFTLE is not so sure about the advanced substrate solutions in the 3-1um range , but in general this is a good way of looking at how the market is breaking out.

ASE 1

IMAPS 50th in Raleigh

Hope to see many of you at this years fall IMAPS meeting which just so happens to be the 50th anniversary of IMAPS and just so happens to be down the road from me in Raleigh NC. As I explained a few blogs ago [see IFTLE 336 “ISHM to IMAPS…” ] IMAPS has been there since the beginning of our industry and it will be fun to see all of those who have contributed to packaging through the years.

IMAPS

 

For all the latest in advanced packaging, see you at IMAPS 2017 and, of course, keep reading IFTLE…

IFTLE 350 DARPA Electronics Resurgence Initiative: Going Beyond Moore’s Law

Tuesday, September 5th, 2017

By Dr. Phil Garrou, Contributing Editor

IFTLE has discussed in detail the coming end of Moore’s Law and the implications that holds for our electronics industry. For instance see IFTLE 300 “ITRS 2.0 – It’s the End of the World As We Know It”,

Well DoDs DARPA has stepped up and is attempting to lead the industry out of the quagmire that is the myriad of options that have presented themselves.

On June 1, DARPA’s Microsystems Technology Office (MTO) announced a new Electronics Resurgence Initiative (ERI) “to open pathways for far-reaching improvements in electronics performance well beyond the limits of traditional scaling”. Key to the ERI will hopefully be new collaborations among the commercial electronics community, defense industrial base, university researchers, and the DoD. The DoD proposed FY 2018 budget reportedly includes a $75 million allocation for DARPA in support of this, initiative. It is reported that in total we are looking at a $200,000MM program.

For details on the ERI see DARPA-SN-17-60 [link]

chappellThe program will focus on the development of new materials for devices, new architectures for integrating those devices into circuits, and software and hardware designs for using these circuits. The program seeks to achieve continued improvements in electronics performance without the benefit of traditional scaling. Bill Chappell, director of DARPA’s Microsystems Technology Office (MTO), which will lead the program, announced “For nearly seventy years, the United States has enjoyed the economic and security advantages that have come from national leadership in electronics innovation…..If we want to remain out front, we need to foment an electronics revolution that does not depend on traditional methods of achieving progress. That’s the point of this new initiative – to embrace progress through circuit specialization and to wrangle the complexity of the next phase of advances, which will have broad implications on both commercial and national defense interests. ”He continued “We need to break away from tradition and embrace the kinds of innovations that the new initiative is all about…”

The chip research effort will complement the recently created Joint University Microelectronics Program (JUMP), an electronics research effort co-funded by DARPA and SRC (Semiconductor Research Corporation). Among the chip makers contributing to JUMP are IBM, Intel Corp., Micron Technology and Taiwan Semiconductor Manufacturing Co. SRC members and DARPA are expected to kick in more than $150 million for the five-year project. Focus areas include high-frequency sensor networks, distributed and cognitive computing along with intelligent memory and storage.

The materials portion of the ERI initiative will explore the use of unconventional materials to increase circuit performance without requiring smaller transistors. Although silicon is used for most of the circuits manufactured today, other materials like GaAs, GaN and SiC have made significant inroads into high performance circuits. It is hoped that the initiative will uncover other elements from the Periodic Table that can provide candidate materials for next-generation logic and memory components. One research focus will be to integrate different semiconductor materials on individual chips, and vertical (3D) rather than planar integration of microsystem components.

The architecture portion of the initiative will examine circuit structures such as Graphics processing units (GPUs), which underlie much of the ongoing progress in machine learning, have already demonstrated the performance improvement derived from specialized hardware architectures. The initiative will explore other opportunities, such as “reconfigurable physical structures that adjust to the needs of the software they support”.

The design portion of the initiative will focus on developing tools for rapidly designing specialized circuits. Although DARPA has consistently invested in these application-specific integrated circuits (ASICs) for military use, ASICs can be costly and time-consuming to develop. New design tools and an open-source design paradigm could be transformative, enabling innovators to rapidly and cheaply create specialized circuits for a range of commercial applications.

DARPA CHIPS

As part of this overall Electronics Resurgence Initiative, DARPA, last week, had their kick of meeting for the CHIPS program (Common Heterogeneous Integration and Intellectual Property (IP) Reuse). We have previously discussed CHIPS here [see IFTLE 323 “The New DARPA Program “CHIPS”…”

The CHIPS vision is an ecosystem of discrete modular, IP blocks, which can be assembled into a system using existing and emerging integration technologies. Modularity and reusability of such IP blocks will require electrical and physical interface standards to be widely adopted by the community supporting the CHIPS ecosystem. The CHIPS program hopes to develop the design tools and integration standards required for modular integrated circuit (IC) designs.

Program contractors include Intel, Micron, Cadence, Lockheed Martin, Northrop Grumman, Boeing, Synopsys, Intrinsix Corp., and Jariet Technologies, U. Michigan, Georgia Tech, and North Carolina State University.

The CHIPS program will tackle digital interfaces and systems and their supporting technologies with the goal of:

- developing common interface standards                                                                                                                                                    - enabling the assembly of systems from modular IP blocks                                                                                                               – demonstrating the reusability of the modular IP blocks via rapid design iteration

CHIPS 1 CHIPS 2

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