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Archive for August, 2017

IFTLE 348: ASE Tech Forum at Nijmegen part 1 – “Advanced Packaging 2017″

Friday, August 18th, 2017

At the recent ASE Tech Forum in Nijmegen chaired by John Marc Yannou, Ivanovik of Yole gave a nice overview of the industry presentation entitled “Advanced Packaging Industry 2017”

In general they report:

  • Growth decline in the main semiconductor driver (smartphones)
  • Stagnating mature markets (PC, tablets)
  • Cost benefits of CMOS scaling have ceased (see figure below). Long time readers of IFTLE have been aware of this trend sine 2011 when we reported Handle Jones of IBS observed the trend at the annual Semi ISS conference [see IFTLE 40 “Samsung 3D IC Wide I/O DRAM and Semiconductor Predictions for 2011”]

yole 1

In the future they predict no single leading driver, but rather a fragmented growing market including autonomous vehicles, vehicle “electrification”, robotics, AI and that general term that IFTLE hates, IoT.

yole 2

In general packaging has gone from:

  • Bridging the gap between semiconductor and PCB level, serving as IC protection and providing a form factor for testability

to

  • Shifting system integration from the die to the package level!

to

  • Packaging serving as the “IC shell” to becoming the performance and functionality enhancer!

They offered the following as their assessment of 2016 advanced packaging wafer split by manufacturer.

yole 3

Total 2016 OSAT revenue is $27.9B vs IDM revenue of $26.8B

They offer the following as 2016 top 25 OSAT revenue. Taiwan now has 55% of production and China is in second place with 18% followed by the US with 17%.

yole 4

Advantage will go to packaging houses which are able to either:

  • Maintain a large portfolio of package architectures and technologies for customers
  • Lead in specialty processes and packaging (i.e. MEMS, LED, image sensor packaging)

Revenue will continue to be driven by FC over the next 5 years while units will be drive by QFN and fan in WLP.

yole 5

For all the latest in advanced packaging stay linked to IFTLE…

 

IFTLE 347: ASE Embedded Packaging Solutions

Sunday, August 13th, 2017

At the recent IMAPS Carolina Chapter meeting Rich Rice of ASE gave an update presentation on “Embedded Packaging Solutions”. Specifically:

  • SESUB- Semiconductor Embedded In Substrate
  • aEASI –Advanced Embedded Active System Integration
  • FOWLP- Fan Out Wafer Level Package

SESUB

- ASE offers SESUB through the JV with TDK

- embedding IC releases surface space for other components or allows reduction in overall substrate size

- short copper connections improves parasitics

- ~ 2 dozen SESUB programs underway

IFTLE 347ASE 1

aEASI

- combining leadframe and laminate technologies

- embedding for power devices                        

- good current capability, i.e. ~ 60A; 1.9W/mm2

- 300um Cu heat spreader on back of die      

 - 32um thick Cu lines for low resistance

- low resistivity Ag nano die attach materials keep processing temp and electrical resistance down

IFTLE 347ase 2

IFTLE 347ASE 3

FOWLP

- die are embedded in a reconstituted plastic wafer that is then processed like a silicon wafer

- FOWLP can provide size/electrical benefits for a wide variety of products including PMIC, AP, RF devices in mobile applications demanding miniaturization and performance.

IFTLE 347ASE 4

For all the latest in Advanced Packaging stay linked to IFTLE…

IFTLE 346 Sony Introduces Stacked Image Sensor with DRAM in Xperia XZ phones

Monday, August 7th, 2017

By Dr. Phil Garrou, Contributing Editor

It has been nearly a decade since Toshiba announced the use of backside TSV’s to miniaturize CMOS image sensors [ see PFTLE “Imaging Chips with TSV Announced for Commercialization” Semiconductor Int., Oct 27th 2007 ; recall Perspectives from the Leading Edge, PFTLE, was the predecessor to IFTLE and ran from 2007 to 2010 in Semiconductor Int magazine before its demise]

More recently, In Feb 2017 at the IEEE International Solid-State Circuits Conference (ISSCC) Sony announced the Industry’s First 3-Layer Stacked CMOS Image Sensor (90 nm generation back-illuminated CIS top chip, 30 nm generation DRAM middle chip, and a 40 nm generation image signal processor (ISP) bottom chip for Smartphones [link]. Sony further revealed that that the CIS is made in a 90 nm, 1 Al, 5 Cu technology, the DRAM is a 1 Gb, 30 nm (3 Al, 1 W) part, and the ISP is a 40 nm, 1 Al, 6 Cu device.

Readers of IFTLE were given this info even earlier [ see IFTLE 272 “2016 3D ASIP Part 1: Pioneer Awards; Sony 3D stacked CIS…” ]

This newly developed sensor with stacked DRAM delivers fast data readout speeds, making it possible to capture still images of fast-moving subjects with minimal focal plane distortion as well as super slow motion movies at up to 1,000 frames per second (approximately 8x faster than conventional products) in full HD (1920×1080 pixels).[link]

At the recent Mobile World Congress, Sony announced adoption of this technology their Xperia XZ Premium and XZs phones, with the Motion Eye camera system capable of 960 fps.

Dick James, writing in EE Times, reports on cross-sections of the rear-facing camera chip which contains the 3 layered stack. The CMOS image sensor (CIS) is mounted face-to-back on the DRAM, which is face-to-face with the image signal processor (ISP). [Link] The cross section below is direct for Sony. Since the DRAM is sandwiched between the CIS and the ISP, the high-speed data has to go through the memory chip to the ISP, and then back-and-forth until it is output through the I/F (interface) block of the ISP, at a conventional speed suitable for the applications processor” reports James who then adds that since the DRAM die also has the CIS row drivers on it, it must be “designed as a custom part, and is not one of the TSV-enabled (TSV = through-silicon via) commodity DRAMs”.

sony 1

James has also shown the TSV layer connections between the two chips (see below). The cross section below shows two layers of TSVs connecting a 6-metal stack in the CIS to the M1 of the DRAM die. They did not have a cross-section of extended TSVs joining the CIS directly to the ISP, though there are TSVs through the DRAM to the top metal of the ISP.

sony 2

In an interesting article by Ray Fontaine of TechInsights [link] he notes that “the development of low-temperature wafer bonding and various wafer-to-wafer interconnect techniques have been key enablers for stacked image sensors. Two-die stacks, comprising a back-illuminated CIS and mixed-signal image signal processor (ISP), have emerged as the dominant configuration for leading smartphone camera chips. The CIS portion can be considered a ‘dumb’ chip carrying only an active pixel array. Most of the signal chain and digital processing is partitioned onto the ISP and systems application processor.”

He then offers the following table comparing technologies that have been implemented since 2013.

TechInsights

 

With Sony’s inclusion of DRAM into the CIS stack, IFTLE can safely predict that Omnivision and Samsung will not be far behind.

For all the latest in advanced packaging, stay linked to IFTLE…