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IFTLE 341 Topics from ECTC 2017: Thin Die Handling; IPD on Glass

By Dr. Phil Garrou, Contributing Editor

This week, we will begin looking at key presentations from the 2017 ECTC in Orlando.

General Comments:

There were a total of 335 presentations in 36 oral sessions at this year’s ECTC. Since 2012 attendance is up ~ 50% to 1438 and professional development course attendance is up from 83 to 203! IFTLE feels this follows the trends that we have been sharing with you for years, i.e. scaling is slowing down and more and more front end practitioners are moving to the back end to develop customized products.

This in turn necessitates attendance at packaging conferences such as ECTC and necessitates front end engineers taking the development courses available at ECTC.

I am personally tired of going to Orlando, that probably just a personal preference since I have been attending since 1985. As an aside, if the meeting gets much larger it will have to move to convention sites since current hotels will not be able to fit the group into their ball rooms for lunch.

In terms of technical content, “fan out WLP” has moved into the forefront in terms of the number of papers addressing this topic, but there were still lots of papers addressing 2.5D, interposers, copper pillars, WLP and bumping, thinning, dicing and molding.

BESI – Thin Die Handling

The importance of high yield thin die handling is getting more and more crucial for advanced packaging options. This applies for stacking with wire bonds/die attach film (DAF), and also for TSV ). Besi Switzerland and IMEC addressed this issue in their paper “Key Properties for Successful Ultra Thin Die Pickup”.

Die stress levels during peeling can still be significantly high, and can lead to die cracking or pickup failure. Avoiding high stress levels involves an understanding of the dynamic interaction of die, wafer tape and the die ejection system. From die bonding point-of-view, four key properties are most important for a successful pickup of thin dies, as shown below : bending stress during pickup, die strength, edge peel force and bulk peel force.

besi 1

Starting the peel process at the die edges is the most critical moment during peeling. Dicing should be done in a way, that the heat-sensitive die attach film on the die backside is not affected. Otherwise, an increased adhesion can occur at the die edges.

Besi concludes that multi stage, multi disc or multi pin ejectors are required for proper handling. These are shown in the fig below. Ejectors with finer mechanical structures like the multi disc ejector result in the lowest stress values.

besi 2

For ultra thin dies, UV curing of the adhesive layer after dicing is very common. This method enables high adhesion during dicing (5 – 20 N/25mm), and reducing adhesion for pickup (< 0.2 N/25mm). In general, the bulk peel force is smaller than the edge peel force. In other words, once the die edges have started to peel off, the rest of the die will peel off quite easily.

The speed of moving ejector parts (needles, discs, stages) that activate the peeling process has to be adapted to the wafer foil properties and die thickness. The higher the required peel energy, and the thinner the die, the lower the process speed must be adjusted.

ASE / Marvell – Is it Time for IPD?

As mobile devices become more functional, they are required to accommodate more frequency bands and meet ever smaller form factor requirements. IPD technology (integrated passive devices). IPD offer smaller for factor and higher performance for RF solutions. For filters, high Q inductors are the key. Glass is a good candidate for substrate because of its low dielectric loss, high thermal stability, high resistivity, and adjustable CTE. Glass also provides the advantage for potential cost effective solutions.

ASE Kaohsiung working with Marvell Santa Clara addressed “Glass Based 3D-IPD Integrated RF ASIC in WLP.”

In a glass base 3D-IPD integrated with RF ASIC the glass wafer acts as a bottom wafer, while the ASIC die is flip chip attached to the frontside of the glass wafer. The ASIC wafer comes with the Cu pillar bump.

The process starts with TGV metallization and filling processes, then, carry on the standard wafer level IPD process to complete the frontside structure. The frontside structure consists of capacitor, re-distribution layer (RDL), and under bump metal (UBM). Then, the wafer is shipped to assembly site for wafer level assembly. Wafer level assembly processes are the chip-to- wafer, for the RF ASIC to attach to bottom glass wafer, and wafer level molding process. After assembly, follows by the backside process to form the 3D inductor and ball pad. Backside process includes glass wafer thinning, and backside RDL and passivation processes. Next step is ball mount and singulation to form the WLCSP. The process flow is shown below:

Marvell 1

Reliability tests confirm that results of SAT and open/short are good, and destructive analysis also show no disconnection issue between TGV and double side metal traces. The high-Q 3D inductor performance was verified through measurement results with two port S-parameter measurement methods with the demonstrated Q factor measured above 60 at 1 GHz for a 3.5nH inductor. 

What’s the Required Size for a Real Industry Driver ?

Recent blogs like IFTLE 322 “…A Period of Uncertainty” have led to questions about what would a really big industry driver look like?

As many of you know, I really don’t consult about the size of markets that currently don’t exist simply because I know, as an ex supplier, that no one, and I really mean no one, knows those answers. I could overwhelm you with example after example of markets being projected too large and too early (It always seems to go in that direction…wonder why??)

When we look at our industry and try to anticipate what will come next we are really always comparing to the two big boys …semiconductors and displays. Those are gigantic, albeit mature, electronic industry segments. I would think these would be the benchmark. I obtained some recent numbers from my friends at Prismark for these two segments, just so we could keep things in perspective, and they are:

Total Semiconductor value in 2016 – $339Bn

Total Wafer Fabrication Value 2016 (excludes chip design, test, package, and profit): $129Bn

Total area processed – 8.2M m2

Total Display 2016: $135Bn (The display market is the panel market, not finished TVs, monitors, etc.)

Total area processed – 185M m2

A few years ago many were betting on Solar to join this group but it did not happen. Ask AMAT how that bet worked out for them. My IFTLE take was that any segment that needed to be propped up by Govt support and needed to have its rivals (coal, nuclear, oil) persecuted by the Govt to get their foot in the door, just was not going to make it long term. Don’t get me wrong, solar works, but just no where near the 11cents/KW hr that I buy electricity at now in NC. We all know that in the end “price is king”.

Next in line was / is IoT (the internet of things). Projections for this market have also bordered on astronomical. In 2010, Ericsson estimated that there would be 50B connected devices by 2020. Cisco soon agreed and then Intel been touting the 50B number since 2014.

Recently Ericsson has revised its estimates down to 28B connected devices by 2021, McKinsey believes will be between 20 – 30B devices by 2020 and Gartner says 21B connected devices by 2020. [link]

These numbers are certainly still large enough to be a major driver, but IFTLE is still doubtful of such huge numbers, how quickly we will reach them and more so of IoT’s overall impact on the advanced packaging market specifically.

I can recall being at meetings where 2.5 / 3DIC were being predicted to be instrumental for implementation of IoT. Now that’s when I really knew that exaggeration had gotten out of hand. As IFTLE has said before, maybe some medical applications will allow for high end packaging solutions, but NOT the everyday sensing that most techies are envisioning will generate the massive IoT data in the future. Those will be low cost solutions with the ultimate low cost packaging for sure.

Fear not, electronics isn’t going away, a new driver WILL eventually appear on the horizon and our industry will continue unabated into the future. That I can promise you…

For all the latest on Advanced Packaging, stay linked to IFTLE…

2 Responses to “IFTLE 341 Topics from ECTC 2017: Thin Die Handling; IPD on Glass”

  1. Dr. Dev Gupta Says:

    4 or 5 years ago people were predicting that 3d stack of DRAM using TSVs and the replacement of PoP was imminent. Adequate performance at lowest cost rules. Cost is directly proportional to physical complexity and the novelty of a technology.

    BTW noticing in this IFTLE an unfortunate tendency to replace the established term Flip Chip used by the Packaging industry by “Chip on Wafer” started by a certain Foundry trying to break into Packaging with expensive new packages of uncertain benefit masked with new nomenclature ! )

  2. IFTLE Says:

    Dev – “chip on wafer” ? Actually I use the generic terms “bumping” and flip chip interchangably… dont ever recall using “chip on wafer” unless it was quoting someone else.

    As many of you recall IBM invented FC, but it was FCT, Unitive and BCB that brought bumping mainstream in the late 1990′s…I was there participating and saw the whole thing…….

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