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Archive for June, 2017

IFTLE 339 Will 450mm Equipment Keep Si the Fine Feature WLCSP Solution?

Tuesday, June 13th, 2017

By Dr. Phil Garrou, Contributing Editor

On the eve of the formal ECTC presentations, the conference held a panel session pitting wafer processing vs panel processing for the low cost production of “high density” fan out WLP.

“In the left corner representing wafer processing are TSMC’s Doug Yu and Nanium’s (Amkor’s) Stefan Krohnert and in the right corner representing panel processing are Deca’s Tim Olsen and IZM Fraunhoffer’s Rolf Aschenbrenner …the referee for this match, representing user groups, is Qualcomm’s Steve Bezuk……Let’s get ready to rumble…”

 

Wafers vs panels

 

Basically the question is: if and when will panel processing tools be fully developed and capable of manufacturing and testing fine L&S (i.e 2um) fan out packages produced in yields similar to silicon wafer lines. If/when this happens, how will silicon foundries counter such results.

Let’s look at some of the key points made by the above parties during this hour plus discussion.

Wafer Processing

- [Yu] InFO leverages his companies core business – i.e Si wafer processing

- [Krohnert] capital for FOWLP is already depreciated whereas there are no panel level processing in place so new capital will have to be expended on newly developed equipment.

- [Yu] Inspection of wafers is a well known process whereas panel inspection has to be developed

- [Yu] technology must be face down so you can package chips of different heights (polish) Face up panel tech cannot do this. …also passives cannot be thinned like chips can be.

- [krohnert] “..a fully loaded high yield wafer line might be cheaper than a partially loaded low yield panel line” he went on to explain that if panel processes FOWLP only reached required yields for low-medium I/O devices there are other ways to manufacture such packages and the remaining “sweet spot” panel business may not be enough to fill panel lines.

- [Yu] landed a solid right to the jaw of his opponents when asked about what the silicon foundry response will be if indeed panel processing is developed and is yielding fine L&S. His response was that TSMC is part of the 450mm development team and although the equipment already developed and purchased by TSMC does not look like it will be processing leading edge node wafers any time soon, such tools and processes could easily be applied for 1-2um features. “This would be low hanging fruit for such tools and processes.” Yu then indicated that a possible plan is to make such a move when they feel the panel processing is ready. He cautioned, though, that this will produce a major oversupply of capacity.

The Referee:

- [Bezuk] the main volume for WLFO is currently for 3-5mm pkgs

- [Bezuk] InFO is currently the thinnest package you can buy today

- [Bezuk] equipment for panels is being developed but having problems like shedding particles during startup which is affecting yield

- [Bezuk] simple FOWLP like codec chips use a single layer of RDL, if multi layer RDL is required FOWLP becomes too costly

- [Bezuk] materials costs for both technologies are ~ 50% of the total.

Panel Processing:

- [Aschenbrenner] panel level processing shows a sweet spot for small-medium I/O devices

- [Olsen] projects a 30% cost advantage for large panel processing

- [Olsen] working with ASE on 300mm round today and panels in the future

- [Aschenbrenner] agreed that panel processing cost reduction will only be achieved when yields are close to the same as for wafers

- [Aschenbrenner] panels appear to need class 100 clean area to achieve yield on fine lines

- [Olsen] agreed that panel equipment is taking a long time to “get clean”

IFTLE concludes that panel processing is still about the “promise” of lower costs. As such it certainly is worthwhile to do the work to find out if this can be put in place.

The major new news item from this panel was certainly TSMC bringing up the potential use of 450mm wafer equipment which would continue to leverage their core business/technologies, if and when it is economically required. Was this shared insight or a clever bluff?

Bar Cohen term

As a point of clarification, Dr. Avi Bar Cohens term of President of the IEEE Electronics Packaging Soc. (EPS) will begin Jan 2018.

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 338 Bar Cohen to Take Over IEEE EPS (CPMT); Ho and Tu Win IEEE Packaging Field Award

Wednesday, June 7th, 2017

By Dr. Phil Garrou, Contributing Editor

As we noted in IFTLE 336, the IEEE packaging society, which has been known as IEEE Components, Packaging and Manufacturing Technology society since 1993 is about to be renamed the IEEE Electronics Packaging Society (EPS).

Bar-Cohen takes over IEEE CPMT

At the Board of Governors meeting just held in conjunction with the 2017 ECTC conference, Avram Bar Cohen was elected as the first President of the newly named society.

Bar CohenDr. Bar-Cohen is currently a Principal Engineering Fellow at Raytheon Corporation – Space and Airborne Systems. Bar-Cohen recently completed six years as a Program Manager in the Microsystem Technology Office at the US Defense Advanced Projects Agency (DARPA). Before that he held several University positions including Chair of Mechanical Engineering at the University of Maryland and Director of the University of Minnesota Center for the Development of Technological Leadership.

He is an internationally recognized leader in thermal science and technology. His current efforts focus on embedded cooling, including on-chip thermoelectric and two-phase microchannel coolers for high heat flux electronic components, thermal control of directed energy systems, and studies of wireless power beaming.

Bar Cohen is a Fellow of IEEE, and is a past Editor-in-Chief of the CPMT Transactions (1995-2005). In 2014 he was honored by the IEEE with the prestigious CPMT Field Award and had earlier been recognized with the CPMT Society’s Outstanding Sustained Technical Contributions Award (2002), the ITHERM Achievement Award (1998) and the THERMI Award (1997and ASME’s Heat Transfer Memorial Award (1999), Edwin F. Church Medal (1994), and Worcester Reed Warner Medal (1990).

Ho and Tu win IEEE Electronic Packaging Field Award

The IEEE CPMT field award was established in 2002 and is presented yearly for “…meritorious contributions to the advancement of all aspects of device and system packaging including microelectronics, optioelectronics, Rf/wireless and MEMS. This is the highest level packaging award in all of IEEE. To view a complete list of past recipients see http://www.ieee.org/awards.

This year Paul Ho, Director of the Interconenct and Packaging Laboratory of the University of Texas and King-Ning Tu professor at National Chio Tung Univ of Taiwan have received this award for “contributions to the materials science of packaging and its impact on reliability, specifically in the science of electromigration” . The patented innovations of Ho and Tun, while at IBM earlier in their careers, overcame the roadblocks caused by electromigration that limited high performance chip reliability. Addressing Al and Cu wire connections and solder bumps their work provided the foundation to understand the science of observed failure mechanisms and guided high volume chip designs and manufacturing processes. They also addressed reliability issues of low-k dielectrics and tin whiskers.

Ho (center) and Tu (right) receive field award from current IEEE CPMT President Jean Trewhella Ho (center) and Tu (right) receive field award from current IEEE CPMT President Jean Trewhella

For all the latest in advanced packaging, stay linked to IFTLE…

 

IFTLE 337 Will Samsung displace Intel in 2017?; Foundry Samsung – A reality; I-Cube

Thursday, June 1st, 2017

By Dr. Phil Garrou, Contributing Editor

Samsung will soon displace Intel

IC insights has announced that if memory market prices continue to hold through 2Q17 Samsung could displace Intel, which has held the #1 semiconductor sales ranking since 1993.

“Using the mid range sales guidance set by Intel for 2Q17, and a modest, yet typical, 2Q sales increase of 7.5% for Samsung, the South Korean supplier would unseat Intel as the world’s leading semiconductor supplier in 2Q17 (see below). [link]

IC insights 1

As we have discussed in IFTLE 332 “Wither Goest the Toshiba NAND Business…” Toshiba is in the process of selling off their memory business to raise cash. At that point all 6 of the 1993 top 10 semiconductor suppliers from Japan will be out of the top 10.

IC insights 2

Samsung Foundry Separates

Late last fall reports from Korea indicated that Samsung would likely spin off a foundry business unit. [link]. “Samsung Electronics’ System LSI business division is largely divided into four segments; system on chip (SoC) team which develops mobile APs, LSI development team which designs display driver chips and camera sensors, foundry business team and support team. According to many officials in the industry, Samsung Electronics is now considering forming the fabless division by uniting the SoC and LSI development teams and separating from the foundry business.”

IFTLE has commented many times over the past 5 years that if Samsung ever focused on a foundry business they would immediately become the #2 foundry supplier and could soon compete with TSMC for the number one spot.

On May 12th Samsung finally announced it will spin off its foundry operation from the System LSI division to create an independent business unit [link]

If Samsung really wants to run this is a seperate entity and compete head on with TSMC, IFTLE recommends they take their packaging capabilities withthem to the foundry because that’s the only way to compete with CoWoS and InFO etc.

Samsung 14nm Network Processor uses 2.5D “I-Cube”

Samsung reported that they have taped out their 14nm Network Processor close collaboration with eSilicon and Rambus [link]. This is based on Samsung’s 14LPP (Low-Power Plus) 3D FinFET process eSilicon’s ASIC and 2.5D design capability and IP solutions, and Rambus’ 28G SerDes solution.

Samsung announced that they will “…keep developing (our) network foundry solution to be a ….total network solution provider aligned with (our) process roadmap from 14nm to 10nm to 7nm.”

On the packaging front, they report that they have named their newly developed full 2.5D turnkey solution, which connects a logic chip and HBM2 memory on an interposer, as I-CubeTM (Interposer-Cube) solution. This 14LPP network process chip is the first product that Samsung applied I-CubeTM solution together with Samsung’s HBM2 memory. The I-CubeTM solution will be essential to network applications for high-speed signaling, and it is expected to be adopted into other applications such as computing, server and AI in the near future.

e-Silicon aded “Our HBM Gen2 PHY, custom flip-chip package design and custom memory designs also helped to optimize the power, performance and area for the project.”

HBM2 Interposer with Silicon or Laminate?

At the Hot Chips conference late last summer Samsung in a proposal for low-cost HBM, Samsung outlined plans to lower the complexity and thus cost of HBM technology.

The savings will come from solutions to the listed challenges.

- fewer TSV will make the stacks easier to manufacture and interconnect

- removing the buffer die will make the stack simpler, but the buffer die customization was one of the original tenants for the memory stacking concept so this is confusing.

- moving from a silicon to a laminate interposer on first glance should reduce costs, and the rest of the industry has certainly listed this as an option, but it is still unclear the impact this will have on performance.

Samsung 1

 

For all the latest in Advanced Packaging, stay linked to IFTLE…