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Archive for May, 2017

IFTLE 335 Catching Up on China and the Wait for the New Industry Driver

Monday, May 22nd, 2017

By Dr. Phil Garrou, Contributing Editor

Catching up on some recent stories of great importance to our electronics industry… and thus packaging. 

SMIC urges Taiwan chipmakers to partner with China-based peers

IFTLE readers are well aware that China is in a “no holds barred” battle to become a major player on the IC fab scene. [See for example IFTLE 316 “YMTC and China’s desire for 3D NAND production”; IFTLE 296 “…China the wild card…”]

Digitimes, quoting Tzu-Yin Chiu, CEO of SMIC, now reports that SMIC is urging Tiwanese chip makers and the Taiwan government to collaborate with mainland China electronics peers. [link]

Chiu indicated that “The IC industries in China and Taiwan could team up as a powerful IC industry supply chain globally”, adding that the Taiwan government should enable China based enterprises to cooperate with their Taiwanese peers.” Taiwan IC fabs including TSMC, UMC and Powerchip have indeed taken China government support to set up production on the mainland.

Chiu also disclosed that SMIC has been developing 14nm FinFET chips and will be starting R&D on 7nm s technology in late 2017.

US Dept. of Commerce – “China Poses Threat to US Dominance in Semiconductor Industry”

In a related story, South China Morning Post is reporting that US Commerce Secretary Wilbur Ross sees the US semiconductor industry as still dominant globally but said he is worried that it will be threatened by China’s planned investment binge to build up its own chip making industry. [link]

Ross said that the Commerce Department is considering a national security review of semiconductors because of their defense implications in military hardware and their general proliferation in devices throughout the economy. Ross reportedly called China’s plans for massive state-directed investments in semiconductor manufacturing capacity under its “Made in China 2025” program, which aims to replace mostly imported semiconductors with domestic products, “scary”.

Commerce Department trade data shows that the “Semiconductors and related device manufacturing” category showed a trade deficit of $2.4B in 2016, with exports of $34.1B and imports of $45.6B which includes non-semiconductor devices such as solar cells and LEDs.

Waiting for the New Driver…Impatiently

Bloomberg is reporting Qualcomm Inc. and MediaTek are both showing slowing sales and declining margins as shown below [link].

bloomberg 1

They point out that this is due to a maturing of the mobile phone industry segment and look to “IoT and automotive” to save things, but are impatient for this new drivers arrival “the IoT should be the next big thing for chipmakers. The problem is that this era has yet to fully arrive, leaving them supplying a smartphone market that’s peaked

For a read on Yole”s take on potential IoT applications before Rozalia Beica”s departure, see IFTLE 227 “Yole’s Beica examines Internet of Things …”

IFTLE is a believer in the general concept of IoT, i.e. Rf transfer of data from inanimate objects, but as we have mentioned before we do not see this as a general boon to advanced packaging since such applications will require the absolute lowest priced packaging solutions, not typical of advanced packaging.

IFTLE considers automotive similarly. Certainly there is no question that there will be more and more electronics built into automobiles, but, based on my career at a major chemical company which had other divisions supplying plastics to the automotive industry, I can tell you that supplying the automotive industry is the antithesis of a high margin business for suppliers. Typically automotive business is used to fill he plant (in the industry this is called loading the plant) which in turn generates lower cost per unit volume which can be used to meet the lowball pricing required to get the automotive business while also increasing margins in other applications using the same materials but accepting a higher profit margin for the supplier.

If anyone out there thinks electronics is a tough industry to play in, try automotive!

Hope to see you all in a few weeks at the ECTC in Orlando.

ectc128

For all the latest in Advanced packaging, stay linked to IFTLE…

IFTLE 334 On High Performance Computing, Chiplets and Interposers

Tuesday, May 9th, 2017

By Dr. Phil Garrou, Contributing Editor

Most of us packaging focused technologists do not traditionally follow what’s being presented at the IEEE High Performance Computing Architectures Conference (HPCA)…but that’s why you follow IFTLE…i.e. to find such material. This year’s conference was held in Austin, TX the first week of Feb. What I want to focus on is the presentation by AMD on “Design and Analysis of an APU for Exascale Computing.”

If some of these concepts look familiar, check out IFTLE 323, “The New DARPA Program “CHIPS.”

The need for ever more computational power continues to grow and exaflop (1018 ) capabilities may soon become necessary. This paper presents the AMD vision for an exascale node architecture for exascale computing including low-power and high-performance CPU cores, integrated energy-efficient GPU units, in-package high-bandwidth 3D memory, die-stacking and chiplet technologies, and advanced memory systems.

Two of the building blocks for this exascale node architecture are (1) it’s chiplet-based approach that decouples performance-critical processing components like CPUs and GPUs from components that do not scale well with technology (e.g., analog components), allowing fabrication in individually optimized

process technologies for cost reduction and design reuse in other market segments and (2) the use of in-package 3D memory, which is stacked directly above high-bandwidth-consuming GPUs. 

The exascale heterogeneous processor (shown below) is an accelerated processing unit (APU) consisting of CPU and GPU compute integrated with in-package 3D DRAM. The overall structure makes use of a modular “chiplet” design, with the chiplets 3D-stacked on other “active interposer” chips. “The use of advanced packaging technologies enables a large amount of computational and memory resources to be located in a single package”. The exascale targets for memory bandwidth and energy efficiency are incredibly challenging for off-package memory solutions. Thus AMD proposes to integrate 3D-stacked DRAM into the EHP package.

AMD -1

In the center of the EHP are two CPU clusters, each consisting of four multi-core CPU chiplets stacked on an active interposer base die. On either side of the CPU clusters are a total of four GPU clusters, each consisting of two GPU chiplets on a respective active interposer. Upon each GPU chiplet is a 3D stack of DRAM. The DRAM is directly stacked on the GPU chiplets to maximize bandwidth. The interposers underneath the chiplets provide interconnection between the chiplets along with other functions such as external I/O interfaces, power distribution and system management. Interposers maintain high-bandwidth connectivity among themselves by utilizing wide, short distance, point-to-point paths.

Chiplets

The performance requirements require a large amount of compute and memory to be integrated into a single package. Rather than build a single, monolithic system on chip (SOC), AMD proposes to leverage advanced die-stacking technologies to decompose the EHP into smaller components consisting of active interposers and chiplets. Each chiplet houses either multiple GPU compute units or CPU cores. The chiplet approach differs from conventional multi-chip module (MCM) designs in that each individual chiplet is not a complete chip. For example, the CPU chiplet contains CPU cores and caches, but lacks memory interfaces and external I/O.

While a monolithic SOC imposes a single process technology choice on all components in the system.

With chiplets and interposers, each discrete piece of silicon can be optimized for its own functions.

It is expected that smaller chiplets will have higher yield due to their size, and when combined with KGD testing, can be assembled into larger systems at reasonable cost (IFTLE note – this is yet to be proven).

It is expected that the decomposition (or disintegration as IFTLE prefers to call it) of the EHP into smaller pieces will enables silicon-level reuse of IP.

(note – this is one of the main drivers of the DARPA CHIPS program …see IFTLE 323)

Thermal Issues ? 

EHP’s in-package DRAMs stay below the 85°C limit. The figure below shows the temperature difference in the bottom-most in DRAM die in a stack (in the package). They conclude that their use of aggressive die stacking should be thermally feasible with air cooling. However, “…more advanced cooling solutions may become necessary as the hit rate of the in-package DRAM improves, more power from the external memory is shifted to the EHP, or if a design point uses a greater per-node power budget.”

amd 2

For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 333 Amkor & Global discuss FOWLP at IMAPS Device Pkging Conf

Tuesday, May 2nd, 2017

By Dr. Phil Garrou, Contributing Editor

Finishing up our look at the IMAPS Device Packaging Conference with presentations by Amkor, Global Foundries and Huan Tien (FCT) on their FOWLP technologies.

Huan Tien

With reported revenue of $972MM, Huan Tian is ranked #6 among global OSATS. They bought FCI in Phoenix in the fall of 2014. For you younger readers, Flip Chip Technology was a JV of Delco and K&S where Pete Elenius, Tom Strothmann and a host of others developed the bumping technology used today in most of the OSATS and foundries globally. They also invented and commercialized the first fan in WLP. For a review of where things stood in 2000 try this excellent review [“Wafer level chip scale packaging (WL-CSP): an overview”   IEEE Transactions on Advanced Packaging ( Volume: 23, Issue: 2, May 2000 http://ieeexplore.ieee.org/abstract/document/846634/]

They have now developed an embedded silicon fan out technology as shown below.

Instead of mold compound, silicon is used as the carrier with KGD embedded and bonded in the wafer cavities. The micro gap between the die and cavity ( ~ 35um) is filled with polymer. Cavities are formed by Bosch etching and are generally ~ 100um deep.

Huan Tian 1

 

They report:

- lower warpage     – higher density RDL capability

- larger CTE miss match to the motherboard

- parts passed all standard reliability tests.

A roadmap for their embedded silicon fan out (eSiFO) is shown below.

huan Tian 2

Amkor

Suresh Jayaraman discussed “silicon wafer integrated fan out technology”. Amkor sees a migration from Flip chip and fan in packaging to FOWLP as shown below.

Amkor 1

Key drivers in the High Perform Computing (HPC) and Mobile markets are shown below. They project that eventually the high density FOWLP segment will be > 70% of the total fan out market.

Amkor 2

Below is their roadmap for high density an out evolution.

Amkor 3

GlobalFoundries

Gaurav Sharma discussed “development of fan out package platform for high performance and Rf Applications”.

Suggested benefits for Rf Performance are shown below:

GF 1

They also shared their roadmap for introduction of high density fan out technology

GF 2

For all the latest in Advanced Packaging, stay linked to IFTLE…