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IFTLE 321 IMAPS 3D ASIP Part 4: SPIL Fan-Out Options; BESI Thermo-compression Bonding Options

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IMAPS 3D ASIP Conference from this past December.

Siliconware

Albert Lan discussed Fan-out from the perspective of SPIL.

Lan showed a nice cartoon depiction of the fan out options of die first, die last and face up and face down as shown below.

SPIL 1

Of special interest is their fan out SiP with metal lid to partition EMI. The FO-SiP requires excellent control of the compression molding process.

SPIL 2

This will allow elimination of substrate and thus thinner packages with better electrical performance as shown below.

Their warpage “adjustment” technique is also of intrest as shown below.

SPIL 3

Besi

Hugo Pristauz of Besi described some essentials of thermal compression bonding (TCB).

Pristauz contends that TCB is used when confronted with issues of warpage, ultra fine pitch and / or thermal stress. He points out that there are actually 3 types of TCB processes as shown below.

Besi 1

 

As we have detailed on IFTLE previously [see IFTLE 108 2012 ECTC 2: NCF, WUF, MUF for tight pitch Assembly], NCF appears to be the TCB process of the future.

Current technology is capable of 10um pitch assembly (C2W face up) which means 2um@3s accuracy. Any attempts to move to 1um pitch would require 200nm@3s accuracy.

A significant issue is maintaining positional accuracy and co-planarity while ramping from cold to hot. Thermal compensation needs to be identified by the bonder (automatically) and recalled from memory during bond control.

EVG

Thomas Urhman of EVG discussed technologies for high performance and high bandwidth Applications.

The interesting slide below examines use of the various debonding techniques vs applications. The debonding techniques use heat, force and light respectively to induce separation from the carrier support.

EVG 1

 

Hybrid bonding, as originally developed by Ziptronix, and as being adopted by Sony for image sensor 3D stacking, requires plasma activation of the surface and tight control of the CMP process. Excess Cu dishing can ruin the bonding. Currently processes using 3-5um pad size at 6-10um pitch are available.

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