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Archive for February, 2017

IFTLE 323 The New DARPA Program “CHIPS”; Amkor Acquires Nanium; GE Licenses SEMCO

Tuesday, February 21st, 2017

By Dr. Phil Garrou, Contributing Editor

CHIPSBack in the late 1970s, there was a TV show in the US called ChiPS which stood for California Highway Patrol. It was poorly written and even more poorly acted. Thank goodness that’s not what we are going to be talking about now.

The research wing of the Defense Department, otherwise known as DARPA, put out a broad agency announcement in Sept 2016 for a program called “Common Heterogeneous Integration and IP Reuse Strategies with the same acronym, CHIPS [BAA-16-62] with an anticipated funding level of ~ $70MM. Multiple award are expected. Final proposal due date was Dec 16th and the estimated start date was reported to be ~ 4 months after proposal submission. The program is being run by Dr. Dan Green in MTO (Microsystems Technology Office).

Pay attention to this program because it has the possibility of creating a paradigm shift in how electronics are done today. The goal is to lower cost and decrease turn around time for military electronics, but design flows that will be created could have major impact on the industry as a whole. As IFTLE has said in the past few weeks, with the end of Moores Law, we are searching for high impact alternatives and this just may be it.

As the BAA describes it, DARPA expects participants to “…leverage existing designs that would benefit from translation to a modular framework in order to enable reuse of captive IP, include commercial IP, or allow faster redesign and update cycles.” A key feature of CHIPS is the establishment of standard interfaces to promote the reusability and interchangeability of modular circuit functional blocks or chiplets. In the first phase of the program the community will “converge on a limited number of interface standards that are broadly useful.”

darpa 1

DARPA CHIPS 1

 

CHIPS consists of 3 technical areas (TA1) focused on modular digital designs; (TA2) focused on modular analog design and (TA3) focused on supporting technologies.

SoC (system on chip) technology has been driving the industry for several decades as further functions were implemented on chip. We are now looking at a reversal of this process. DARPA called it “dis-aggregation” IFTLE prefers to call it “disintegration”. Once in place it wil allow you to replace only functions that need to be upgraded and not have to redesign and remanufacture the whole SoC chip. Whatever you want to call it, it looks like exciting times are ahead and you will be sure IFTLE will keep you informed on all new CHIPS info as it becomes public.

Amkor Acquires Nanium

OSAT consolidation continues as Amkor and NANIUM have announced that they have entered into an agreement for Amkor to acquire NANIUM. NANIUM is based in Porto, Portugal, has 500+ employees and sales of ~ $40 million in 2016. Terms of the transaction were not disclosed.

“Amkor’s technology leadership, substantial resources and global presence coupled with NANIUM’s best-in-class WLFO packaging solutions will accelerate global acceptance and growth of this technology worldwide.”

The acquisition of NANIUM will strengthen Amkor’s position in the fast growing market of wafer-level packaging for smartphones, tablets and other applications. NANIUM has developed a high-yielding, reliable eWLB based WLFO technology, and has successfully ramped that technology to high volume production. NANIUM has shipped ~ 1B WLFO packages off their 300mm Wafer-Level Packaging (WLP) production line.

Adding this to their SLIM and SWIFT technologies which are moving into HVM Amkor seeks to expand the manufacturing scale and broaden the customer base for such fan out technology solutions.

GE Licenses SEMCO their Embedded Chip Packaging Technology

GE Ventures and Samsung Electro-Mechanics (SEMCO), have announced a patent license agreement where SEMCO will license GE microelectronics packaging patent portfolio, covering the fabrication of substrates embedded with electronic circuits. This patent portfolio was developed by GE Global Research and Imbera Electronics Oy (now GE Embedded Electronics Oy) as part of the GE focus in power electronics over the last decade. [link 1] They seek to provide significantly improved electrical performance (for example, reduced parasitics), increase functional density of the electronics circuits by more than a third, and can increase efficiency by over 10%.

GE Ventures has already licensed IP to TAIYO YUDEN for fabricating substrates embedded with electronic circuits in late 2014. “TAIYO YUDEN and GE are working towards the commercialization of next-generation wirebondless, embedded electronics circuits including Si-, SiC- and GaN-based wirebondless embedded electronics circuits with the technology and the IP provided by GE Ventures. “[link 2]

GE Ventures has also licensed SHINKO ELECTRONICS their advanced embedded packaging solution for power electronics called Power Overlay (POL) to “…industrialize the packaging platform and transition POL to manufacturing for GE and others.” [link 3]

For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 322 SEMI ISS 2017: A Period of Uncertainty?

Tuesday, February 14th, 2017

By Dr. Phil Garrou, Contributing Editor

SEMI’s annual Industry Strategy Symposium was held at its usual site, Half Moon Bay, CA a few weeks ago.

It may just be me, but it seemed like this year’s overall message was one of an industry searching. IFTLE thinks the end of scaling and the public indications that 450mm does not appear to be moving forward has left the industry wandering a bit. Yes, there is excitement over IoT, but the exact way that this will play out in terms of low cost connectivity solutions and the inherent security dangers are not yet clear. For an industry that for the past few decades has had everything laid out on roadmaps this may be a bit disconcerting, but to IFTLE it is now significantly more exciting because the future is not as clear.

Is the following the semiconductor roadmap for the future?

IFTLE 1

With that said, here are some of the highlights of 2017 ISS from IFTLE perspective.

Linx Consulting

Corbett of Linx Consulting looked at the state of the wafer fab materials segment. They indicated that the total market for semiconductor materials in 2015 was $18.5B with most of the top players being in the wafer and gas businesses.

linx 1

The top 11 supplies have ~$12B sales. Removing the wafer suppliers leaves the following top 10 suppliers with categories of materials broken out as follows.

linx 2

 

As IFTLE said many years ago, consolidation in the semiconductor industry would lead to similar consolidation of their suppliers (materials and equipment). Linx presented the following materials merger list.

linx 3

International Business Strategies (IBS)

Our old friends at IBS note that:

- Apple semiconductor value in 2016 will be $9.6B

- Apple is driving advanced features including move to 10 and 7nm

- Smaller features will continue to give lower power and higher performance but now at a cost premium

- Chip scale packaging will enjoy significant growth

- 3D NAND will show high growth

- smartphones will continue to lead demand at least through 2025

- Growth of IoT will accelerate after connectivity to the cloud becomes very low cost and business models are established for monetizing value of data

Specific areas of high growth are shown below:

IBIS 1

Western Digital / Sandisk

Chen presented an interesting history of NAND and concluded that this new conversion of 2D NAND to 3D NAND is more complex than past 2D to 2D conversions and will generate a period of limited cost reduction in the industry. In the past, 2D to 2D scaling transitions took 4-5 quarters but now 2 to 3D is expected to take 14 to 16 quarters!

WD 1

GlobalFoundries (GF)

Patton of GlobalFoundries sees 5G as disruptive technology, which will transform today’s communication architecture.

GF 1

Patton also pointed to packaging as the alternative to silicon scaling (readers certainly know that IFTLE agrees).

GF 2

For all the latest in Advanced Microelectronic Packaging, stay linked to IFTLE…

IFTLE 321 IMAPS 3D ASIP Part 4: SPIL Fan-Out Options; BESI Thermo-compression Bonding Options

Wednesday, February 8th, 2017

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IMAPS 3D ASIP Conference from this past December.

Siliconware

Albert Lan discussed Fan-out from the perspective of SPIL.

Lan showed a nice cartoon depiction of the fan out options of die first, die last and face up and face down as shown below.

SPIL 1

Of special interest is their fan out SiP with metal lid to partition EMI. The FO-SiP requires excellent control of the compression molding process.

SPIL 2

This will allow elimination of substrate and thus thinner packages with better electrical performance as shown below.

Their warpage “adjustment” technique is also of intrest as shown below.

SPIL 3

Besi

Hugo Pristauz of Besi described some essentials of thermal compression bonding (TCB).

Pristauz contends that TCB is used when confronted with issues of warpage, ultra fine pitch and / or thermal stress. He points out that there are actually 3 types of TCB processes as shown below.

Besi 1

 

As we have detailed on IFTLE previously [see IFTLE 108 2012 ECTC 2: NCF, WUF, MUF for tight pitch Assembly], NCF appears to be the TCB process of the future.

Current technology is capable of 10um pitch assembly (C2W face up) which means 2um@3s accuracy. Any attempts to move to 1um pitch would require 200nm@3s accuracy.

A significant issue is maintaining positional accuracy and co-planarity while ramping from cold to hot. Thermal compensation needs to be identified by the bonder (automatically) and recalled from memory during bond control.

EVG

Thomas Urhman of EVG discussed technologies for high performance and high bandwidth Applications.

The interesting slide below examines use of the various debonding techniques vs applications. The debonding techniques use heat, force and light respectively to induce separation from the carrier support.

EVG 1

 

Hybrid bonding, as originally developed by Ziptronix, and as being adopted by Sony for image sensor 3D stacking, requires plasma activation of the surface and tight control of the CMP process. Excess Cu dishing can ruin the bonding. Currently processes using 3-5um pad size at 6-10um pitch are available.

For all the latest in Advanced Packaging, stay linked to IFTLE…