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Archive for January, 2017

IFTLE 320 3D ASIP: Amkor Multi Die Packaging; Brewer‘s New Temp Bonding Sys

Tuesday, January 31st, 2017

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IMAPS 3D ASIP Conference 2016.

AMKOR

Mike Kelly of Amkor updated their status on 2.5 and 3D multi die packaging.

amkor 1

High density solutions on 2.5D interposer technology are focused on data center, networking, HPC and military.

Amkors 2.5D production readiness:

- MEOL wafer thinning and backside processing

- 300mm TSV line in K4 … K5 starting Jan 2017

- SPC control

- automated wafer handling

- yield > 97.5 % (die level)

- Assembly

- production in K4 (85K parts built to date)

Yields > 98%

Comparison of Signal Routing for high density technologies:

SWIFT production readiness:

- internally qualified

- ready for small body high volume production in Q2 2017 in K5

- large body process in development

Routing capabilities are compared below: Slim > 3x SWIFT > 3X FC

amkor 2

Yole

Emilie Jolivet of Yole shared information on memory stacks. Their look at memory stack IP concludes that the area has been dominated by Samsung, Hynix, Micron/Elpida as you would expect.

yole 1

UCLA CHIPS Program

We have previously discussed the Subu Iyer CHIPS program at UCLA [ see IFTLE 301 “Are Silicon Circuit Boards in our Future?”]

As described before, the plan here is to “disintegrate” (system partition) into functional blocks. These blocks would become a standardized IP library which would be available later as reusable IP. These chiplets (or dielets – the community has not decided what to call them) would then be recombined on a high density silicon fabric to fabricate the desired module. Iyer has calculated that these small (< 3 x 3mm) chiplets would require ~ 5um L/S to interconnect them. Lot of similarities to the current. In many ways this approach is similar to the CEA Leti chiplet activity and the DARPA CHIPS program which we shall look at soon.

UCLA 1

Brewer Science

When you think about temporary bonding you certainly think of Brewer Science who has been developing products for this technology area for over a decade.

brewer 1

Through the years they have developed products for several potential debonding schemes:

brewer 2

Their latest development is a two part system called “thermo+ cure” bonding where a thermoplastic layer (~ 2um) first encapsulates the device features followed by a curable layer (~60um; 150-200 °C). Debonding, occurs at the thermoplastic / cured layer interface as shown below. No part of the structure, after curing, can flow during backside processing.

brewer 3

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 319 Mike Ma to Amkor; 3D ASIP Part 2: Image Sensing – Sony, Tessera, SMIC

Tuesday, January 24th, 2017

By Dr. Phil Garrou, Contributing Editor

Ma to Amkor

Mike MaThis week, I can announce that Dr. Mike Ma, with 23 years in the microelectronics industry, has moved from SPIL to Amkor as Taiwan Country Manager. Mike served as Vice President of Corporate R&D and Spokesperson at SPIL. Mike holds M.S. in Materials Engineering from Northeastern Univ and PhD in Material Science and Engineering from North Carolina State Univ.

It’s great to see someone who has maintained his keen interest and knowledge in technology attain such a lofty position. Many of you might remember Mike during his earlier days at UMC.

We all know that when consolidation occurs like the ASE – SPIL merger (I know legally this is not being called a merger, but you also know IFTLE always calls a spade a spade) savings are achieved by staff reduction, especially at the higher levels – redundancy they call it. In this case IFTLE is confident that my friends at ASE have made a major mistake letting Mike leave. IFTLE message to Amkor – good pick up!

CMOS Imaging at 3D ASIP 

This year’s 3D ASIP put a special emphasis on CMOS image sensing.

It was the fall of 2007 when Toshiba first announced the commercialization of TSV in a CMOS image sensor (CIS). [see IFTLE 89 “Advances in CMOS Image Sensing”]

In 2012 Sony announced that it was separating the pixel section (containing the back-illuminated structure pixels) from chips containing the circuit section for signal processing, and oxide bonding the layers and then connecting them with TSV. [see IFTLE 172 “Sony TSV Stacked CMOS Image Sensors Finally Arrive in 2013”]

Seperation of pixels from circuits using oxide bonding and TSV  Seperation of pixels from circuits using oxide bonding and TSV

Earlier this year [see IFTLE 303 “Sony Introduces Ziptronix DBI Technology in Samsung Galaxy S7”] a Chipworks teardown of the Samsung Galaxy S7 revealed the first use of the Ziptronix (now Tessera) Direct Bond interconnect (DBI) technology rather than prior oxide –oxide bonding with subsequent TSVs connecting through the oxide interface (In most circles this is referred to as “HYBRID BONDING” and does not require TSV.

sony 4

So it seems only fitting that this years 3D ASIP image sensing plenary presentation was by Tetsuo Nomoto, Sr General Mgr of Sony’s mobile imaging systems business. Sony sees several key applications for CMOS image sensor technology:

sony 2

Nomoto indicates that the next generation will include stacked DRAM chips to achieve “ 5X faster scan out and storage data, improve distortion and reduce 1/F bandwidth” and then incorporating a DSP into the stack to 3 Layered modules with customized staked DRAM will be shown at the next IEEE ISSCC.

sony 3

The audience really perked up when Nomoto indicated that Sony believes such technologies will be instrumental to furthering robotics and robotic manufacturing.

sony 5

During the Tessera presentation by Paul Enquist, they described the new “hybrid bonding process as follows:

Tessera 1

Since Sony is currently in production with 6um pitch and Tessera is currently capable of 1.6um pitch in demonstration vehicles, they feel they are close to pixel level interconnect technology.

Tessera 2

Yole reports that back side stacked and back side stacked hybrid technology will take over ~ 60% of the marked by 2021.

Yole 1

Roc Blumenthal described SMICs CMOS image sensor capabilities.

SMIC 1

Credit where credit is due

Lastly, that great cross section of the TSMC InFO package that I used in IFTLE 218 (shown below) inadvertently had the source cropped off on insertion into the blog. Full credit should go to Prismark consultants and Bingamton Univ. for this great tear down and cross section. Further details can be found in Prismark’s Semiconductor and Packaging Report Q3 2016.

InFO

For all the latest on Advanced Packaging, stay linked to IFTLE…

 

IFTLE 318 2016 IMAPS 3D ASIP: The Expanding World of Fan-Out Packaging

Tuesday, January 17th, 2017

By Dr. Phil Garrou, Contributing Editor

The 13th 3D ASIP conference was held this year under the umbrella of IMAPS. This year’s meeting was chaired by Alan Huffman (Micross), Mark Scannell (CEA Leti) and Mitsumasa Koyanagi (Tohoku Univ) . I remained on board to help with the program organization and to transition the conference to IMAPS.

(L to R) Scannell, Koyonagi, Garrou, Huffman (L to R) Scannell, Koyonagi, Garrou, Huffman

We’ll first take a look at the “Advances in Fan-out Packaging” course by Beth Keser of Qualcomm (see recent changes below) and next week begin with plenary lectures provided by Tetsuo Nomoto of Sony, Jean Michailos of ST Micro, Bill Chen of ASE and Subu Iyer of UCLA and then other key presentations.

(L to R) Keser, Nomoto, Michailos, Chen and Iyer (L to R) Keser, Nomoto, Michailos, Chen and Iyer

Advances in Fan-out Packaging

Who better to teach the fan-out packaging course than the co-inventor of RCP while at Freescale. 20 years ago Beth was coating BCB wafers for Ted Tessier at Motorola, today she is the go to person for fan out packaging in the world. For those keeping track of such things, reports are that Beth has just become Director of Packaging at iCDG at Intel in Munich. This is the mobile business they bought from Infineon a few years ago that designs devices for mobile phones. You’ll remember them as the inventors of eWLB fan out packaging!

I won’t give away too much of her course since many of you have not yet seen the live presentation, which I recommend you all do to gain a complete understanding of what this technology is all about.

Lets start by offering up the IFTLE comment that I have used many times “ALL PACKAGES ARE FAN OUT EXCEPT FAN IN WLP” meaning lead frame packages, BGAs ect are all fan out.

By now we are all used to the FO-WLP process flow developed for the Infineon eWLB as shown below. With the proliferation of reconstituted, mold compound based FO-WLP, such processes have become known as face down, chips first.

keser 1

Reconstituted Fan-out has really taken off recently as it has been developed for multi-die , i.e SiP applications and PoP (package-on-package) applications. It has also developed capabilities to achieve much higher densities in both face down and face up process flows. For PoP applications Keser point out that it:

- eliminates warpage and co-planarity issues since there is no substrate

- offers PoP height reduction

- eliminates stress on the die from bump interconnect (maybe but there is still stress – see InFO X-sect below)

Second generation products have been coming out in rapid progression but Keser cautions that only the InFO is currently available. – Xilinx / SPIL “SLIT” [IFTLE 215]

- DECA “M series” [IFTLE 124, 175, 267]

- TSMC “InFO” [IFTLE 283, 305, 311]

- Amkor “SWIFT and SLIM” [IFTLE 243, 309]

- ASE [IFTLE 22, 269]

I will not go over all of these, but have given you links back to previous discussions in IFTLE

Of interest continues to be the upcoming ASE merger with SPIL and their announced investment to scale up the DECA FO-WLP technology [IFTLE 292].

I have commented in IFTLE 292 that DECA and InFO appear to be very similar technologies by polishing the surface during pillar expose step to produce a very flat surface for the RDL fabrication. Keser reports that TSMC is in production with 5/5 (L/S). Many of the speakers are showing InFO cross sections taken from analysis of the Apple A10 (TSMC has still not published process flow or cross section) I have included it below for those readers who have not seen it yet. This is a PoP package with memory on the top (side by side to thin the package down) and the processor below. Note the overall bow in the structure!

Keser 2

In short, “Fan-out packaging” is certainly expanding its technology capabilities and appears to be capable of taking significant package market share in the future.

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 317 IEEE 3DIC Part 2: 3D Processing at Tohoku Univ & Extreme Thinning Options for Vias Last Pkging

Monday, January 9th, 2017

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IEEE 3DIC Conference.

Tohoku Univ

Koyanagi and co-workers at Tohoku Univ studied the use of Ti as a 3D TSV barrier layer.

Cu was substituted in the early 2000s for Al interconnect wiring which no longer meet the resistivity requirements in the aggressively scaled technology nodes. Cu, which has low electrical resistivity has proved itself as a potential interconnect material, only if necessary barrier layers are in place.

The most serious concern with Cu as interconnect material is the formation of midgap defects in active Si, since it diffuses fast into the Si. Owing to this, the minority carrier life time is reduced several orders even at 200 °C. Moreover during this diffusion process since Cu travels through SiO2, the insulation nature of SiO2 is degraded which can result in premature dielectric breakdown leading to device failure. The well known method to prevent Cu diffusing into SiO2 and then in Si is to sandwich an amorphous metal layer between the Cu and SiO2. Required properties of a good barrier layer are low internal film stress, high thermal stability and low resistivity. Metals with high melting points are known to have larger activation energy for the diffusion to take place.

Although Ta is best suited as a barrier material based on melting point, Ta has more integrated film stress than Ti film, i.e. a 200 nm-thick sputtered Ta film possesses internal stress of 1.4 GPa, whereas the stress in a similar thickness Ti film is 0.8 GPa . Internal stress is the main cause for the delamination of sputtered Ta films. Thus Ti is a better barrier layer based on internal stress.

One way to improve the barrier performance of Ti, is to use a Ti/TiN structure as barrier layer, but TiN has a large resistivity (p~270 µW.cm) .

The Tohoku group has found a simple method to improve the barrier ability of Ti layer is to anneal the TSV structures in vacuum at temperatures up to 400 °C. This results in a significant improvement in leakage current characteristics for SiO2 dielectric. TiSix has been identified at the interface between Cu and SiO2 during the sputter deposition.

Another presentation by Tohoku Univ examined the reduction of keep-out-zone in 3DIC by local stress suppression with negative-CTE filler.

The thinning of the IC chips leads to low flexural rigidity of IC chips. In addition, the CTE of the underfill material is larger than that of metal microbumps. In other words, the underfill material shrinks more compared to metal microbumps. IC chips are bent by this shrinkage after the 3D integration process. This CTE mismatch induces local bending stress in thinned Si chips, and in turn effects the MOSFET electrical performance in thinned Si chips.

In general, SiO2 or Al2O3 filler have been introduced into the underfill to reduce the CTE of underfill. High density filler is required to realize a CTE close to the value of the microbumps. However, it is difficult to use the conventional density underfill for 3D IC with fine pitch microbumps due to its high viscosity. What’s required is a low viscosity low CTE underfill.

The Tohoku group suggests a negative CTE material as the filler to suppress the local bending stress. They used manganese nitride-based negative-CTE material as filler. The CTE of this material is -45 ppm/K at the temperature from 65 °C to 100 °C.

Tohoku 1

IMEC / SPTS

IMEC & SPTS reported on extreme wafer thinning optimization for via-last applications.

One of the approaches for 3D-SOC W2W bonding is schematically shown below. After oxide bonding, the top wafer can then be thinned and backside via-last TSV contacts can be created to connect electrically to both the top and the bottom wafers.

SPTS 1

 

Two wafer thinning approaches were investigated targeting a 5μm top wafer Si final thickness:

  1. A) A combination of grinding to 25μm followed by an extensive 20μm Si CMP step
  2. B) a combination of grinding to 50μm followed by a short Si CMP step (1μm Si removal) and 44μm Si dry etch process based on a NIR end point detection system performed in an SPTS Rapier XE system.

They conclude that the safest approach combines grinding and a fast Si dry etch which, combined with an in-situ end point detection, enable a very precise and stable etch stop process at the desired

thickness. Moreover, a cost model has shown that this approach is 50% more cost effective as compared to an integration flow that would involve a long and expensive Si CMP step.

Amkor

For those who havn’t seen it, Amkor has announced that they have completed product qualification of their Silicon Wafer Integrated Fan-Out Technology (SWIFT) WLFO technology for mobile, networking and SiP applications. SWIFT incorporates an “RDL first” process that allows SWIFT wafers to be built and yielded ahead of the assembly process. SWIFT is targeted for production in the second half of 2017 at K5 in Incheon, South Korea.

Amkor SWIFT

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 316 YMTC and China’s Desire for 3D NAND Production; Patent Activity In the 3D Memory Space

Tuesday, January 3rd, 2017

By Dr. Phil Garrou, Contributing Editor

Happy New Year to ALL from IFTLE !

A little diversion from chip packaging this week. Let’s take a look at China’s YMTC. As we have explained several times on IFTLE, semiconductors have been China’s biggest import for more than a decade. Forbes reports that China buys about half of the world’s chips (> $200B / yr), producing the biggest gap in their trade deficits—even ahead of oil. [link]

If your not in the memory business you probably have never heard of YMTC, but they are about to become the largest NAND memory producer in China.

Yangtze River Storage Technology.

China created the country’s largest chip maker last week, taking a giant step towards Beijing’s plan of becoming less reliant on foreign technology.

Under government direction, Tsinghua Unigroup, China’s largest chip designer has acquired a majority position in XMC, one of China’s leading chip makers. The new holding company is called Yangtze River Storage Technology.

One type of semiconductor China is particularly focused on is 3D NAND for mobile devices and solid-state drives. In 2015 YMTC announced that they were working with Spansion to co-develop 3D NAND technology. [link]

At the September 20th China IC Industry Development Seminar / China IC Manufacturing Annual Conference in Xiamen, Dr. Simon Yang, general manager of YMTC announced that they are “…striving to … enter large-scale memory field based on 3D NAND”. [link]

YMTC 1

 

Yang explained that “…both DRAM and NAND Flash are applied to many products …. However, from the perspective of business operation, whether to start with DRAM or 3D NAND is both a technical issue and an economic one. If we go for DRAM, two extra problems pop up: first, rivals have massive depreciated products; second, demands for DRAM grow relatively slow. Therefore, I think M&A is a better choice for DRAM field. In contrast, flash memory cell technology is evolving from traditional floating gate to closed-loop-gate charge trap, and charge trap is one of the technological strengths of YMTC. 3D NAND is a major breakthrough for YMTC, and what we need to do now is to make 3D charge trap memory. The structure features high performance and low cost, which presents a great advantage.” Yang also indicated that 3D NAND would replace 2D NAND quickly and make profits during the depreciation period.

 

XMC announced a major NAND memory fab construction in March of 2016 which is expected to begin production in 2018 and reach a 200k wafers per month capacity within a decade. [link]

However it should be noted that Gartner recently published a report analyzing the probability of semiconductor projects in China, and estimated that there’s just a 40% probability of XMC being able to produce 100,000 wafers by 2020

It is felt that YMTC will likely require manufacturing technology from established international players such as Intel, Samsung, SanDisk, SK Hynix and Toshiba. Since those are too expensive to acquire, some feel YMTC remains focused on Micron. YMTC’s Tsinghua Unigroup tried to buy Micron for $23B last year but were blocked by the U.S. government. [link]

Forbes reports rumors that YMTC is still trying to work out a technology licensing and collaboration deal with Micron although this is being denied. [link]

Issues such as allowing China to buy into the US electronics industry are set to be examined by the Semiconductor industry working group of the Council of Advisors on Science and Technology (PCAST) in Washington. [link]

It is expected that Trump will take an even harder stance on such acquisitions to protect the US manufacturing which employs more than 250k workers and is the third-largest source of manufactured exports, according to the U.S. Commerce Department.

Yole Developpement

For those of you that missed it, Yole has recently released an interesting chart on the Issued IP in the 3D stacked memory field. As could be expected Samsung, SK Hynix and Micron/Elpida lead on the IP front.

584bd036

For all the latest in advanced chip packaging, stay linked to IFTLE…