IFTLE 310 SEMICON Taiwan Part 4: TSV Based Packaging – SPIL, Amkor, EVG
By Dr. Phil Garrou, Contributing Editor
Continuing our look at advanced packaging activity at the 2016 SEMICON Taiwan. This week let’s look at some presentations that focused on TSV based packaging.
SPIL – TSV in IC Packaging
Mike MA of SPIL reviewed the status of TSV in IC Packaging. His summary of current TSV usage is shown below:
- TSV in CIS – Sony
- TSV in MEMS/Sensor
- 3D IC with TSV – only in High Band Width (HBM) DRAM
-Hynix, Samsung start HBM-1 LVM in 2015
-HBM-2 in 2016
- Advantage proven, cost still high
- 2.5D IC with TSV Si Interposer
- 2010 Xilinx debuted 1st product group (FPGA)
- 2015: AMD rolled out 2nd product group (GPU+HBM)
- 2016 nVidia GP100 with HBM-2
- Renewed interest for high end networking, VR/AR
SPIL currently doing 40um pitch on their ubumps as shown below.
SPIL is a proponent of the so called “chip on wafer last” process flow as shown below:
Other interesting comments by Ma include:
“The glass interposer has come and gone due to a lack of ecosystem”
“Fine line organic interposers keep delaying delivery of 5um L/S with still unknown costs. PCB insustry needs to invest in sub 5um L/S”
“Fan out packaging is capable of 2um L/S x 2 layers, but larger package size (> 15 x 15mm sq) will be challenging”
Amkor – Large Die Assembly with TSV Packaging
JY Khim discussed large die assembly technology in TSV packages. He notes the following points about their multi-die platforms:
CoS Process Flow
- No molding • Interim test available
- Mold sensitive components OK • Shared infrastructure with FCBGA
Initial interposer warpage affects the PCB + interposer warpage. For the successful top die attach warpage minimization of interpose is important. Tuning the Inorganic C4-side passivation layer can reduce interposer warpage.
He compares the CoS to the CoW process below:
In the CoW Process, there are no warpage risks in top die attach on interposer regardless of die size.
Khim showed the following table containing Amkor 2.5D CoW experience.
EVG – Chip Stacking in High Volume
For those looking for a good comparison of Samsung vs Hynix stacked memory cross sections, Wimplinger of EVG offered us the following figure and table comparing the two.
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