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Archive for September, 2016

IFTLE 305 Where is Samsung Widecon?? ; TSMC InFO found in iPhone 7

Tuesday, September 27th, 2016

By Dr. Phil Garrou, Contributing Editor

Samsung Widecon Technology

Samsung introduced us to their Widecon technology in 2014 [link] and it was predicted that this 3D TSV technology linking memory to processor would be introduced in the Exnos 6 generation.

widecon

 

Dick James (Chipworks) recent assessment of the tear own of the Galaxy note 7 [link] tells us that

the application processor that drives this phone is the Exynos 8 Octa (Exynos 8890), similar to the Galaxy S7 and S7 edge. It has an eight-core CPU, with four Samsung designed cores that can run at 2.3 GHz, and four ARM Cortex A53 cores operating at up to 1.6 GHz. Stacked on top of the CPU in the usual package-on-package (PoP) stack, is 4 GB of Samsung LPDDR4 SDRAM. Now that we have 20 nm DRAM processes, the dies are small enough that they are packaged in a 2 x 2 x 2 configuration. The four stacks of two 4-Gb memory dies are mirror-imaged, on both the vertical and horizontal axes.

exnos 8

So – it looks like we are still going to have to wait for the commercial introduction of widecon.

TSMC InFO becomes commercial reality

For several years ow, rumors have been rampant that TSMC scaling of their InFO packaging technology was focused on acessing the highly lucrative Apple iPhone market. For instance see IFTLE 283 “Will Packaging make the Difference for TSMC?”

InFO

While a definitive process flow for InFO has not been publically described by TSMC, in IFTLE 261 we reported on a rumored InFO process flow which consists of (1) copper pillar plating on the die, (2) die placed face up on tape, (3)molding to generate reconstituted wafer, (4) polish down to reveal tops of pillars, (5) RDL processing on this polished surface. The capability for finer features than standard fan out packaging reportedly comes from the more planar starting surfaces and better control of the photo processes.

We have also pointed out rumors that ASE would second source an InFO process [see IFTLE 292]

Now a Chipworks teardown confirms the presence of the A10 Fusion chip, manufactured by TSMC with a reported 3.3 billion transistors, in the iPhone 7 link]. Chipworks confirms that the process is a TSMC 16nm finfet based.

Apple A10

“The A10 sits below the Samsung K3RG1G10CM 2-GB LPDDR4 memory. This is similar to the low power mobile DRAM as the one we found in the iPhone 6s. Looking at the X-rays we see the four dies are not stacked, but are spread out across the package. This arrangement keeps the overall package height to a minimum. Assembled in a package-on-package assembly with the A10 InFO packaging technique reduces the total height of PoP significantly”

So the InFO rumors were in fact correct and this in turn will fuel the drive towards HVM of fan out packaging.

ASE Providing SiP for Apple

We had previously noted that ASE was the sole supplier for Apple’s custom-designed SiP modules for used in the Apple Watch. [See IFTLE 238 “ASE & the Apple watch, …”]

Digitimes now reports that ASE, through its Shanghai-based subsidiary Universal Scientific Industrial (USI), has obtained SiP orders for Wi-Fi, fingerprint sensor and force touch modules used in the recently-released iPhone 7 [link].

ASE holds a nearly 80% stake in USI, which has been engaged in backend services for SiP modules.

For all the latest information on Advanced Packaging, stay linked to IFTLE…

 

IFTLE 304 Renesas Acquires Intersil; Intel’s Knights Landing: An Update

Tuesday, September 20th, 2016

By Dr. Phil Garrou, Contributing Editor

Renesas Acquires Intersil

Consolidation continues with the latest deal announcement of Renesas buying Intersil for $3.2B beating out Maxim who was known to be seeking a similar deal [link]. Renesas reportedly aims to complete the deal by June 2017. The acquisition will need to win approval from the US Committee on Foreign Investment, which scrutinizes deals for potential national security issues.

Renesas was created in 2003 from the chip-making units of NEC, Mitsubishi Electric and Hitachi . It is the world’s largest auto semiconductor maker in 2014,[ one of the world's largest makers of semiconductor systems for mobile phones, the world's largest maker of microcontrollers 9 controls nearly 40 percent of the global market for microcontroller chips used in automobiles), and the second largest maker of application processors. Its automotive and industrial businesses accounted for 70% of its revenue in 2015. The combination with Intersil is expected to result in better products for in-vehicle entertainment, battery management and safety systems [link].

Intersil, headquartered in Milpitis CA, formed in 1999 when Harris Corp spun off its semiconductor business. In 2014 it had ~1000 employees and revenue of $562MM. It is known for power management ICs and precision analog technology for applications in industrial, infrastructure, mobile, automotive and aerospace. The company supplies power IC solutions including battery management, computing power, display power, regulators a d controllers and power modules; as well as precision analog components such as amplifiers and buffers, proximity and light sensors, data converters, timing products, optoelectronics and interface products. They are a major supplier to the military and aerospace industries

Intel Knights Landing

We first discussed Intel’s Knights Landing in IFTLE 198 [link].

The Knights Landing (KNL) chip is the first commercial processor with very high bandwidth MCDRAM memory (Intel’s name for Microns HMC memory cubes) right next to the CPU in the same package, and the first integrated high speed main memory on any class of Xeon processor. Intel is now apparently able to ship Knights Landing processors in volume with the announcement that they will be shipping several variants of the Knights Landing X86 processor starting September 2016.

Intel disclosed he memory hierarchy of Knights Landing last year, explaining how the mix of local MCDRAM on the Knights Landing package and DDR4 memory that is on the motherboard (but controlled from on-chip memory controllers) like regular servers can be used in different ways, depending on the workload.

Intel 2

The performance jump from the Knights Corner coprocessors to the Knights Landing processors ranges from somewhere between 2.6X and 2.9X with the price only rising by 1.4X to 1.5X.

Intel expects to ship more than 100,000 Xeon Phi units this year into the HPC market. More than 30 system makers are reportedly going to use these Knights Landing processors [link].

Intel is clearly taking as little more time to ramp up the yields on the 14 nanometer processes used to etch the latest Xeon Phi chips, and given that at more than 8 billion transistors per die, it is also the largest chip that Intel has ever made.

intel 1 300mm KNL Wafer

Hynix Building up CMOS Image Sensor Capability

Our discussions in IFTLE 303 on the status of CMOS Image sensor technology had little to say about SK Hynix.

Recent reports from Korea indicate that SK Hynix is going to mass-produce their 13 MM pixel CIS at their 300mm factory M10 in Icheon Korea, in 2017. Because of the size of this CIS, it is believed that SK Hynix could not manufacture at a profit at 200mm. [link]

In October of 2007 Hynix entered the CIS business. In 2008 Hynix acquired Siliconfile, a CIS fabless manufacturing company. Until now, SK Hynix had been supplying CIS with < 5MM pixels.To increase profitability, it has been attempting to increase the percentage of 8MM pixel products to Samsung, Huawei, LG, and other Smartphone manufacturers for their low and medium priced Smartphones.

According to TSR (Techno Systems Res) total sales from global CIS markets in 2015 were about $9.2B. SK Hynix market share of 3.7% stands 6th behind Sony (44.8%), Samsung Electronics (16.5%), OmniVision (13.2%) ON Semi (Aptina Imaging, 6.1%) and Canon (5.3%).

Reader Input on Lester the Lightbulb ( i.e. the Govt. forcing Incandescent technology out of the market )

lights

After reading IFTLE 300 a reader sent in the following picture he took at a Chinese restaurant in Portland Maine.

The lighting fixture over one of the tables seemed rather dim and on further investigation he found two burned out compact florescents (CFL) and an incandescent burning brightly. Certainly, we do not know when any of the bulbs were inserted into the fixture, but after reading IFTLE 300 the reader said this made him laugh out loud or as the younger folks say LOL.

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 303 Sony Introduces Ziptronix DBI Technology in Samsung Galaxy S7

Tuesday, September 13th, 2016

By Dr. Phil Garrou, Contributing Editor

It has been awhile since we last checked in on the CMOS Image sensor (CIS) community to see what the latest advances in packaging were [see IFLE 172 [link], 244 [link], 272 [link] and 278 [link].

For those that need to catch up on the technology roadmap, Toshiba was the first to commercially implement CMOS image sensors with backside TSV last technologies in 2007 ( this was covered thoroughly by my predecessor blog PFTLE which was unfortunately scrubbed from the internet when “Semiconductor International “ went out of business. This technology is well explained by CEA Leti [link].

Many of us stated in 2007 that further advances could be obtained by removing the CMOS circuitry to a separate layer and forming a true 3D chip stack, but the technology implementation had to wait while the industry first converted to back side imaging technology.

“Backside Imaging” – BSI

With a conventional front-illumination structure, the metal wiring above the sensor’s photo-diodes impede photon gathering. A back-illuminated structure (figure below) increases the amount of light that enters each pixel due to the lack of obstacles such as metal wiring and transistors that have been moved to the reverse of the silicon substrate [link].

Back side illumination

 

Back Side Imaging – stacked

The next generation, as expected, combined both BSI and stacking. Conventional CMOS image sensor technology creates the pixel function and analog logic circuitry on the same chip. The motivations for stacked chip CIS include: optimization of each function in the stack, adding functionality to the stack and decreasing form factor.

Since the pixel section and circuit section are formed as independent chips, each function can be separately optimized, enabling the pixel section to deliver higher image quality while the circuit section can be specialized for higher functionality. In addition, faster signal processing and lower power consumption can also be achieved through the use of leading process for the chip containing the circuits.[link]

stacking

 

So, where do things stand commercially?

The 2014 image sensor market was estimated by Techno Systems Research as shown below.

market

 

Sony

Sony is clearly leading in commercializing the latest CIS packaging technologies.

In 2012 Sony announced the Exmor RS, Stacked CMOS back-side illuminated sensor, where the supporting circuitry is moved below the active pixel section, giving ~ 30% improvement to light capturing capability [link 1] [link 2].

The first generation Sony BSI-Stacked chips employed via-last TSVs to connect pads from the Sony-fabricated, 90 nm generation CIS die to landing pads on a Sony-fabricated, 65 nm generation ISP. The die stack was partitioned such that most of the functionality of a conventional system-on-chip (SoC) CIS was implemented on the ISP die; the CIS die retained the active pixel array, final stage of the row drivers, and comparator portion of the column-parallel ADCs

Some of the biggest names in tech use Sony sensors: The iPhone 6 camera has a Sony sensor, as does the Samsung Galaxy S6, Motorola phones, Nikon DSLRs, and Olympus mirrorless cameras. [link]

Earlier in 2016 it was reported that there are two versions of the Samsung Galaxy S7. One has a Samsung stacked ISOCELL sensor (S5K2L1) and the other a special Sony stacked sensor (IMX260) [link].

The recent Chipworks teardown of the Samsung Galaxy S7 with a Sony IMX 260 revealed BSI stacked technology [link 1]. Furthermore it revealed the first reported use of the Ziptronix (now Tessera) Direct Bond interconnect (DBI) technology rather than prior oxide –oxide bonding with subsequent TSVs connecting through the oxide interface [link 2]. This BSI-stacked DBI technology is possibly the next step in the CIS roadmap.

The Chipworks cross-section (see below) reveals a 5 metal (Cu) CMOS image sensor (CIS) die and a 7 metal (6 Cu + 1 Al) image signal processor (ISP) die.  The Cu-Cu vias are 3.0 µm wide and have a 14 µm pitch in the peripheral regions.  In the active pixel array they are also 3.0 µm wide, but have a pitch of 6.0 µm. Note that in the images we’ve included we do see connections from the Cu-Cu via pads to both CIS and ISP landing pads.

Sony DBI

 

Omnivision

Omnivision was the first to sample BSI in 2007 but costs were too high and adoption was thus very low.

In 2015 Omnivision announced their OV 16880 a 16-megapixel image sensor built on OmniVision’s PureCel-S™ stacked die technology [link].

Samsung

Samsung’s first entrant into stacked technology with TSV was also at 16MP with the Samsung S5K3P3SX in late 2014. The CIS die is face-to-face bonded to a 65nm Samsung image signal processor die and connected with W based TSV. The CIS die is fabricated on a 65nm CMOS process with 5 levels of interconnect as shown below, courtesy Chipworks.

Samsung

ON Semi (Aptina)

In early 2015 On Semiconductor (Aptina) introduced its first stacked CMOS sensor the AR 1335 with 1.1µm pixels. It resulted in a smaller die footprint, higher pixel performance and better power consumption compared to their traditional monolithic non-stacked designs. They announced that it would be introduced in commercial products in late 2015. [link]

Olympus

In late 215 Olympus announced the OL 20150702-1 a new 3D stacked 16MP CMOS image sensor [link]

For all the latest on Advanced IC Packaging, stay linked to IFTLE…

IFTLE 302 Amkor Denies Takeover Rumors: BCB Team Wins Amer. Chem. Soc. Award; IMEC’s Beyne Reviews Via-Middle TSV Technology

Wednesday, September 7th, 2016

By Dr. Phil Garrou, Contributing Editor

Amkor Denying Takeover Rumors

Amkor finds itself denying rumors published in Digitimes that there is a takeover bid from Chinas Nantong Fujitsu [link]. If true, Nantong Fujitsu would become the largest OSAT in China as well as the second largest in the world, trailing only ASE.

Taiwan’s Central News Agency has also reported that there is speculation that Nantong wants to buy Amkor [link]

Nantong Fujitsu Microelectronics Co., provides IC assembling and testing services to the semiconductor industry in China. The company offers DIP, SOP; BGS, FC and WLP for automotive devices, memory products, analog ICs, microcontrollers, wireless/RF and analog devices; portable products such as cell phones, data storage systems, notebook computers, and pagers.

Nantong Fujitsu acquired an 85% share of AMDs Penang Malasia and Suzhou China packaging facilities for $371 MM earlier in 2016. [link]

Although Amkor is denying the rumor, such an offer would fit with he previously discussed China 2020 plan to become a major player in packaging [ see IFTLE 296 “…China the Wild Card…” ]

BCB Team Wins American Chemical Society (ACS) Award

The American Chemical Society (ACS) has just announced that a team of current and ex-employees of Dow Chemical have been awarded the ACS award for team innovation for their development and commercialization of Benzocyclobutene (BCB) dielectric [link].

The team, which consisted of Phil Garrou (yours truly), Bob DeVries, Carol Mohler, Eric Moyer and Ted Stokich, worked together to define and scale up a commercial product from a Central Research curiosity.

The award is for work done some 25 years ago, when the Dow team, partially under a DARPA contract, developed a photosensitive BCB formulation which was incorporated into the bumping and wafer level packaging processes developed by FCT (Flip Chip Technologies – Ultra CSP) ) and Unitive (Extreme CSP) and later licensed and practiced by most of the major Taiwan and Korean OSAT houses. At the time, current generations of PI failed to produce manufacturable processes and in the early 2000’s, before new generations of PI and PBO were developed to meet these needs, BCB based components were being used in nearly every cell phone produced in the world.

BCB also revolutionized the MANTECH defense industry by allowing Triquint, Teledyne, NGAS, Raytheon, MA-COM and many others develop multilayer interconnect for their GaAs, GaN and InP processes [link].

Triquint

For those that are interested the history of BCB was summarized in the article “Development and Commercialization of BCB for Microelectronic Applications” by Garrou et. al., in The World of Electronic Packaging and System Integration , B. Michel and R. Aschenbrenner Eds., ISBN 3-932434-76-5. 

IMEC

In the July issue of IEEE Trans. CPMT (p. 983) IMEC’s Eric Beyne reviewed via middle TSV technology development [link].

This paper discusses the key technological aspects of via-middle Cu TSVs, The 3-D integration concept and the wafer front and backside process technology for a 5μm x 50μm Si TSV. A very nice review of TSV formation, exposure and the impact of TSVs on devices.

The via-middle process flow consists of two main modules: 1) the via-middle process between FEOL and BEOL processing and 2) the backside thinning and via reveal process.

Via Middle Process

The via-middle TSV process consists of integrating the TSV module between the end of the FEOL process (typically the formation of W contact metal to devices) and the first damascene Cu interconnect layers. The thermal limitation for processing is, therefore, in the range of 420 –450°C.

The IMEC baseline TSV is a 5-μm diameter, 50-μm deep Si etched TSV. The oxide liner is deposited using a TEOS/O3 pulsed CVD process with a target thickness of 200 nm at the TSV bottom.

As a Cu diffusion barrier layer, 5nm PVD Ta is used. As PVD is highly non conformal, this requires a 120–140nm thick Ta layer on the frontside of the wafer. Cu PVD is used as a Cu seed plating layer. To achieve a sufficiently thick Cu seed at the bottom of the via, an 800–1000nm thick Cu PVD deposit is required on the wafer surface area. This seed layer allows for Cu electrochemical deposition (ECD) and voidless filling of the vias.

After filling a 5 × 50μm via, the thickness of Cu deposited on the wafer surface is 3μm. The actual copper diameter is ∼4.9μm at the top and 4.3μm at the bottom of the TSV. To stabilize the Cu in the TSV and remove impurities after plating, a high temperature anneal is performed before Cu CMP resulting in Cu grain growth and a stable Cu microstructure. Finally, CMP is used to remove the Cu overburden, the Ta barrier layer, and the oxide liner.

IMEC process flow

The main challenge for scaled TSVs is, however, the deposition of a Cu diffusion barrier layer and a Cu electroplating seed layer.

Fully conformal plasma enhanced ALD oxides offer a clear advantage when scaling the TSV diameter. In addition, these dielectrics reduce the thickness of the oxide deposited on the wafer surface by 50%, greatly reducing the oxide liner CMP process time.

As the aspect ratio of the TSVs increases with diameter scaling, the use of PVD for barrier/seed deposition becomes more difficult. ALD deposited barriers are shown to be highly effective for scaled TSV since they can reduce the overall TSV process costs by reducing the deposited layer thickness on the wafer surface by ~10× and, therefore, reduce the CMP time.

Wafer Backside Flow

The Si wafer has to be thinned to enable backside contact to the embedded via middle TSV structures. This requires temporary bonding of the TSV wafer on a carrier substrate, wafer thinning, and a TSV via-reveal process.

Wafer thinning is performed by mechanical wafer grinding. Mechanical thinning results in backside silicon damage, stress, cracks, and dislocations therefore, after grinding and wafer cleaning some of

the backside Si is further thinned using either wet or dry methods. After slightly recessing the Si surface with respect to the backside revealed TSV, the oxide liner is still present on the top of the exposed TSVs. In order to avoid possible backside Cu contamination on the thin Si wafer, a backside SiO/SiN passivation layer is deposited. This has to be performed at relatively low temperatures (<200 °C) as the thin wafer is supported by a temporary carrier using a polymeric glue material.

A backside CMP process step exposes the Cu of the TSVs for further backside processing (e.g., metal redistribution, solder microbumps, and so on).

For all the latest in Advanced Packaging, stay linked to IFTLE…