Part of the  

Solid State Technology

  Network

About  |  Contact

IFTLE 299 Siliconware’s Ma Discusses Die Stacking Options for 2.5D

By Dr. Phil Garrou, Contributing Editor

Continuing our look at IEEE ECTC 2016:

Siliconware – Die Stacking and Integration Options with TSV Based Si Interposers

At the recent IEEE ECTC Conference in Las Vegas, Mike Ma of Siliconware compared various die stacking and integration options with TSV Si interposers. From his perspective there are four main stacking platforms for 2.5D IC in advanced packaging. They are shown in the figures below.

In the first method known as Chip on Chip (CoC) on substrate the silicon interposer is fully processed and then multiple active chips are stacked on the silicon interposer, followed by assembly of chip module on the substrate.

The interposer is diced and attached to a silicon carrier which is coated with temporary adhesive film. The carrier provides handling and warpage control capability, i.e. the silicon interposer warpage can reportedly be controlled to within 10um during high reflow peak temperature. After that, the top die can be sequentially attached onto interposer with flux and joined together via mass reflow then followed by an underfilling process. Then the silicon carrier is de-bonded and the individual chip module attached onto blue tape film frame and ready for substrate assembly just as usual traditional FCBGA process.

In the second method known as Chip on Substrate (CoS), the silicon interposer is fully processed with TSV, metal layers, u-bumps, Backside Via Reveal (BVR) and C4 bumps. The processed silicon interposer is then assembled on the substrate followed by assembly of the multiple active chips onto the interposer.

In CoS, the interposer, ( ~ 100um thick) is die bonded to an organic substrate followed by assembly of top multiple active chips. If the substrate warpage is opposite the interposer (interposer warped up and substrate warped down is usual) , there are risks of electrically open or short failures happened after die bonding process because C4 bump height can’t overcome the gap change between TSI and substrate during the die bonding thermal excursion. Thermal compression bonding (TCB) is used to keep a stable gap between the interposer and the substrate during the die bonding process. In addition, Non-Conductive Paste (NCP) or Anisotropic Conductive Paste (ACP) are used.

SPIL 3 CoC vs CoS

Chip on Wafer before TSI backside process (CoW_first) involves attaching the top active chips on front side micro-pads of silicon interposer before the silicon interposer backside bumping process.

After micro bump bonding, underfilling and molding the wafers are ground down to expose the chip tops. The wafers are then flipped and temporarily bonded to a support wafer, the interposer vias exposed and bumped. The modules are then de-bonded from the carrier to a tape ring. Finally, the modules are FC BGA assembled on the organic BGA substrates

In the Chip on Wafer after TSI backside process (CoW last) single or multiple top dies are attached to the interposer wafer after the interposer has been fully processed including front side u-bumps process, backside via revealing process, backside re-distribution layer and final C4 or Cu pillar bumping process.

After interposer is prepared to receive chips to top surface, it is flipped and supported on a carrier for backside reveal, RDL and bumping. It is then flipped onto a second carrier and he chips mounted, underfilled and molded as before.

SPIL 3 CoW first vs last-2

Comparing to the CoW first process with TSV, die bonding assembly portions are the same, but there are differences in the interposer fabrication. Instead of completing micro-bumps process first, RDL and PSV are implemented first and followed by UBM process. Since TSV-less platform has no interposer in its final form, the carrier can be either glass or silicon. After the carrier bonding process, instead of the usual backside reveal process, the TSV-less interposer will be partially removed by mechanical grinding followed by wet etching to completely remove silicon portion and stop on the remaining passivation layers. The passivation layer is then patterned to expose contact areas for further C4 bumps. Further assembly including the chip module on substrate processes are the same as described for CoW first.

Ma compared the chip stacking options in the chart below.

SPIL 3 Comparison of chip stack options

Editorial correction: In IFTLE 298 IFTLE inadvertently assigned credit for the “20um Pitch Thermo Compression Copper Pillar Bonding” work to IMEC instead of rightful authors at IME. This should have been corrected by now, but we did want to offer our apologies for this error.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

Leave a Reply