IFTLE 294 ECTC 2016: IMEC Discusses Economics of TSV Implementation Options
By Dr. Phil Garrou, Contributing Editor
Continuing our look at the 2016 IEEE ECTC conference.
IMEC – Economics of TSV Implementation Options
IMEC discussed their conclusions about the integration cost of TSVs for TSV middle vs TSV last processing. A 3D cost model developed at IMEC was used to analyze the cost of the different TSV integration approaches with different dimensions investigated for each flow.
The main difference in this step between the TSV middle and TSV last flow is that the TSV middle lithography is processed at a FEOL-fab compatible tool. In the case of TSV last an OSAT-fab compatible lower-cost tool can be used. This difference results in a TSV litho step cost which is approximately 30% more expensive for the TSV middle flow compared to TSV last flow. Furthermore, no difference on the lithography cost is observed due to different TSV dimensions.
Si TSV etch
The processing time for TSV etch depends on the TSV depth and the TSV aspect ratio. Smaller depth TSVs have faster etching times (for example the 5×50 vs. the 10×100 TSV process). In addition, TSVs with more aggressive aspect ratio have slower etching times (the 3×50 TSV middle compared to 5×50 or the 5×50 TSV last compared to 10×50).
TSV liner processing
Following the opening of the TSV hole in silicon, an insulating oxide liner layer is deposited. In the case of TSV middle, different liner deposition approaches are applied, depending on the aspect ratio of the via. In the case of an aspect ratio up to 1:10 a TEOS oxide is deposited. As the TSV aspect ratio becomes more aggressive (for 3×50 and 2×40 TSVs), a more conformal liner layer is required with higher uniformity in the liner thickness along the TSV. Therefore, a PEALD oxide deposition approach is preferred to achieve a liner thickness of 100nm, capped with 30nm SiN layer.
In the case of TSV last, the liner needs to be opened (etched) at the bottom of the via prior to further processing, therefore a highly conformal layer is required. For this reason a PE-ALD oxide deposition is used for all TSV geometries processed with the TSV last approach.
TSV liner opening (for TSV last flow) In the case of TSV last process flow, the oxide liner layer at the bottom of the TSV should be opened after deposition to allow for a conductive path towards the metal layers at the TSV bottom. This is one of the differentiating steps between the TSV middle and TSV last flows. Longer processing times (resulting in smaller tool throughput) are required for the narrower TSV diameter sizes.
TSV Barrier and Cu Seed processing
The first steps towards metallization of a TSV structure are the deposition of a barrier layer to prevent Cu diffusion, followed by a deposition of a Cu seed layer that will allow the Cu filling of the TSV through electroplating. Different deposition options are considered for different TSV sizes . In the case of TSV middle with aspect ratio 1:10 (i.e. 10×100 and 5×50), a PVD Ta barrier layer followed by a PVD Cu seed layer can be applied. As the TSV diameter is scaled further and the TSV aspect ratio becomes more aggressive, alternatives such as ALD processing are required. ALD deposition of 12nm TiN has been demonstrated as a successful barrier layer for a 3×50 TSV middle structure. The barrier and seed layers should be removed by CMP after the TSV processing flow. The cost of the CMP process depends on the thickness of the deposited layers. Therefore, the thin layers deposited by ALD can offer an advantage from a cost perspective when the processing cost of the CMP is also considered.
TSV Cu plating and impact on CMP
Plating time and material cost for the TSV filling depends upon the depth and the diameter of the TSV structure. TSV plating results in an overburden of Cu plated on top of the entire wafer area that needs to be removed by CMP. The Cu CMP process has two stages: (i) bulk Cu polish that is relatively fast and removes most of the plated Cu and (ii) fine Cu polish that is slower and clears the remaining Cu traces from the wafer surface, including the Cu seed layer.
The overall processing flow cost can now be compared for different TSV geometries as shown in the figure below.
In the case of the TSV last processing, the additional costs for the PE-ALD liner, etching the TSV liner within the via, and the backside CMP result in higher processing cost for the TSV last 5×50μm flow by up to 10%.
In the figure below it is demonstrated that scaling the TSV size and the TSV pitch is possible while keeping the processing cost under control. This is achieved by replacing the thicker PVD deposited layers used in the larger TSV geometries with thinner ALD layers for the scaled TSV sizes. Although the processing cost for the ALD layers is higher, the cost for CMP polishing of these thinner layers is lower. This tradeoff helps to control the processing cost as the size and pitch of TSV is scaled from 5×50 down to 3×50 and 2×40 TSV sizes.
Overall it has been shown that main cost contributors for TSV processing are the CMP, the deep Si etch, and the barrier and seed deposition steps.
IMEC – Bumpless Process for 10µm Pitch Assembly
IMEC detailed the use of Damascene processing to achieve a bump-less assembly process for sub 10um pitch interconnects.
Microbumps and high density TSV pitches enable high density interconnects between two or more chip stacks for different applications. However, the mechanical stability of microbumps, bump height uniformity, microbumps under-cut during seed and barrier wet etching, high aspect ratio lithography process, dicing and handling issues and difficulty in thermo-compression bonding (TCB) alignment and stacking for fragile microbumps in 10um pitch range ae serious concerns.
In the IMEC bumpless process UBM in the bottom die is embedded in BEOL dielectric and is fabricated in by damascene processing enabling less bump height variation, smooth UBM surface and thus pitch reduction. Schematic of the bump-less process concept is shown below. The top die which contains UBM and solder, the UBM is plated in dielectric followed by Sn plating in resist. After stripping resist and seed/barrier wet etching, polymer (CA6001B from Hitachi ) is coated and planarized by CMP or surface planer. After Sn plating and seed etch, microbumps were embedded in a spin coated polymer followed by a soft bake step. For planarization, CMP and surface planer tools were used. Polymer acts as support material for planarization and also as underfill material for 3D stacking.
During fast TCB bonding, the polymer starts to reflow and bond to the oxide followed by Sn / Cu reaction and IMC formation and final polymer cure.
Processing is on-going in IMEC with 5um pitch TSV and bump for die to die, die to wafer and wafer to wafer bonding applications.
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