IFTLE 293 Sarda Voltage Regulators; ECTC 2016 – Copper Pumping; Copper Pillar on Embedded Trace
By Dr. Phil Garrou, Contributing Editor
Sarda Heterogeneously Integrated Power Stage
Sarda, UTAC and AT&S announced at the recent Int Symp on 3D Power Electronics, Integration and Manufacturing Symposium that they would be using UTAC’s “3D SiP” technology (based on ECP technology from AT&S) to deliver small, fast voltage regulators for use in data centers.
Sarda’s Heterogeneous Integrated Power Stage (HIPS) technology replaces Si switches with GaAs switches in voltage regulators which reportedly increases switching frequency by 10X, improves transient response by 5X and reduces size by 80%. This in turn can reportedly reduce data center power consumption by 30%.
Continuing our look at the 2016 ECC presentations:
Osaka Fine Feature Electrodeposition Res Center – Copper Pumping
Kondo from the Fine Feature Electrodeposition Research Center in Osaka discussed his solutions for copper pumping. We have known for years that the use of silicon vias (TSVs) causes copper extrusion during copper annealing due to the mismatch of the thermal expansion coefficient of Cu and Si. This extrusion can cause damage to the interconnect above it, as shown in the figure below.
Beyne and co-workers at IMEC developed a solution for avoiding this damage by annealing the TSV at >425 °C and then CMP’ing the resultant copper protrusions before building the layers of on chip interconnect.
The Small Feature Electrodeposition Lab has now reportedly developed an additive “A”, which restricts the copper pumping phenomena and thus eliminates the need for CMP. A comparison of pumping with and without additive A at 450°C is shown below.Pumping at 450°C (a) room temp; (b) without additive “A” at 450°C ; (c) room temp ; (d) without additive “A” at 450°C
The resistivity of electrodeposited copper TSV after 450℃ annealing for the wiring is only 1.09x that of conventional electrodeposited copper.
Initial investigations of the mechanism of this reaction point to 100nm carbon deposition into the triple point of the copper grains which causes unit cell contraction upon annealing .
Amkor – Copper Pillar on Embedded Trace
The continuing push toward miniaturization in both planar & stack-up dimensions, has driven the use of chip-scale packages (CSP) in consumer microelectronics.
The state of the art method for joining die and substrate is currently using solder-capped copper pillars. The pillar and solder are previously plated onto the die through wafer level processing. The advantages of copper pillar technology have been well documented and include greater reliability by inhibiting electromigration , as well as enabling fine pitch interconnects.
There have also been advances on the substrate side where thinner packages are the goal. One
enabling technology has been the development and use of Embedded Trace Substrates (ETS), where the top-layer metal is embedded into the dielectric material instead of being deposited on top of it. This results in a near-planarity of the dielectric material and the top-layer of metal as shown in the figure below.
The advantages of ETS include a lower profile, potential layer reduction and reportedly lower cost. Substrate manufacturing costs and stack-up height are both reduced due to the absence of a core material. Layer reduction can take place due to removal of restrictive core-layer design rules.
Warpage is a real concern in the assembly of packages with ETS, but for applications where warpage can be properly managed, the combination of copper pillar bonding on ETS offers low-cost, thin solutions for packaging advanced devices.
While the near-planarity of metal traces with the surface of the substrate in ETS is effective at reducing the risk of bump-to-trace shorting, there is a corresponding increase in the risk of electrical opens especially as L/S shrinks. Amkor has developed a model to test for interconnection reliability between copper pillar bumps and ETS bond pads, based on design parameters and in-process variables. The critical recess depth of the ETS bond pad is identified as a key parameter linked to interconnection success. Reducing the risk of non-wets requires attention to design and processing during substrate manufacturing, bumping, and assembly.
For all the latest on 3DIC and other advanced packaging stay linked to IFTLE…