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Archive for July, 2016

IFTLE 296: The 2016 ConFab – China the “Wild Card”; HBM Close Up; Comparing High Density Packaging Technologies

Tuesday, July 26th, 2016

By Dr. Phil Garrou, Contributing Editor

By now every web site from the MIT review to Popular Mechanics (yes, seriously) has picked up the release of the last ITRS roadmap and it’s conclusion that Moore’s Law or more precisely “scaling,” as we have known it, are a thing of the past. I will let the dust settle and dedicate IFTLE 300, my milestone, to discuss this milestone.

But for now, taking a respite from the powerful 2016 ECTC conference, let’s take a look at activities at the ConFab that occurred in June.

IC Insights –IC Industry Status

Bill McClean gave his annual look at the state of our industry. His numbers (shown below) show us coming back to pre 2015 values, although IFTLE’s gut feel is that we will be lucky to surpass 2015 numbers. I base this on the now well accepted data that shows our electronics industry has a 96% correlation factor with the overall GDP. It’s nice to have a rosy outlook, but the GDP just isn’t going anywhere lately and even 2% growth may be overly optimistic.

IC insights 1

 

Equally as interesting is the role of China in this economy. In past blogs I have called them the “wild card” in any economic outlooks. They are pursuing the microelectronics industry so strongly because they are currently manufacturing only 13% of the ICs they consume (2015). The Govt has poured billions into funds to try to reverse this.

McClean reports the following 3 phase strategy:

IC insights 2

We are clearly in the 3rd phase now where they are attempting to gain share in the electronics industry by mergers and acquisitions.

ic insights 3

Although attempts to buy Micron, WesternDigital/Sandisk and Fairchild have not worked out, many other mergers / acquisitions / JV’s have as shown below.

IC insights 4

 

TechInsights – Where the money is being made and HBM Close up

Kevin Gibb from TechInsights had an interesting point to make about where the money is being made and some great cross section photos of Hynix HBM memory stacks.

First, looking at where TSMC and UMC generate their sales, we see that TSMC is much more highly invested in the latest nodes, i.e. 28 and 20nm vs UMC. Also interesting that 180 and 130nm are generating more sales for TSMC than 90 and 60nm.

TechInsights 1

 

We are all aware by now of the infamous Hynix HB memory stacks which have become the mainstay of 2.5D memory products like the AMD R9 Fury. The photos below are some of the better close-up cross sections that I have seen.

TechInsights 2

The 5.5um Cu filled TSVs are on 40um pitch and show a 9um KOZ (keep out zone)

 

Intel – Enabling IC Scaling, Miniaturization and System Integration through Adv Packaging

Islam Salama of Intel joined the bandwagon that some of us reached years ago when it became clear that Moore’s Law WAS coming to an end. That is – future product advances / differentiation will come from advanced packaging technologies.

He offered the following slide to support his premise that packaging substrates are becoming an integral part of product performance.

Intel 1

Even more interesting was this comparison of the densities achievable with some of today’s more popular high density packaging technologies. He concludes that panel level technology and die last approaches offer a path for technology scaling and affordability.

Intel 2

For all the latest in 2.5/3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 295 Advances in FO-WLP at 2016 IEEE ECTC

Wednesday, July 20th, 2016

By Dr. Phil Garrou, Contributing Editor

Continuing our look at IEEE ECTC 2016. Let’s examine some of the activity in the FOWLP arena.

ASE

At the recent ECTC conference, Bill Chen of ASE proposed categorization of fan out packaging.

While the initial driver for fan-out packaging like the Infineon e-WLB was to increase available IO for niche baseband applications, the main driver now is clearly to achieve multi chip packaging.

ASE 1

 

Chen now proposes we categorize FOWLP options as follows based on chips first, chips last, multichip or stacked chips (PoP):

ASE 2

DECA – Adaptive patterning for FO WLP

FO-WLP enables size and performance capabilities similar to Wafer-Level Chip- Scale Packaging (WLCSP), while extending the capabilities to include multi-device system-in-packages, with lower costs than 2.5D interposer technologies. But – Adopting these new technologies for single die and multi die system-in-packages requires more advanced design methodologies and tools than traditionally used in traditional WLP.

In a fan-out process the key step is the creation of a reconfigured wafer or panel. First copper studs are formed on the native device wafer over the bond-pads, and then the wafer is singulated. A pick-and-place machine then attaches the dies face-up to a carrier with a temporary adhesive. Then, the carrier and dies are over-molded, the temporary adhesive is removed, and the front of the panel is ground to reveal the copper studs. After this process, called panelization, a first via layer (VIA1), redistribution layer (RDL), second via layer (VIA2), and under-bump metallization (UBM) are formed using processes similar to WLCSP.

Two main challenges prevent widespread adoption of wafer-level fan-out technology are warpage and die shift during processing. Warpage is caused by the mis-matched CTE between mold-compound and silicon and can be addressed using structural approaches, such as the fully molded structure, or by tuning process parameters. Die-shift is the accumulation of die position error from chip-attach tolerances and movement during over-molding. Tuning process parameters such as pick-and-place force can help minimize shift, and movement due to molding is often predictable enough to compensate for during chip-attach. However, the total die shift can still range from 30 μm to 45 μm with rotation up to 0.3°on a high-throughput machine.

The die-shift problem has limited traditional FO-WLP from widespread adoption. In order to meet industry requirements, FO-WLP must be processed with high-throughput chip-attach machines, typically resulting in shift distributions that cannot be handled by traditional processes. Additionally, these processes cannot handle finer pitch connections to the die with wider shift distributions

The DECA technology derived to do this is called “Adaptive Patterning”. In this manufacturing process, an optical scanner is used to measure the true position of each die after molding, and a uniquely generated fan-out design is applied to each package. One design technique, adaptive alignment, shifts and rotates the first via and RDL layer to match the die location. Another technique, adaptive routing, utilizes a fan-out RDL design with sections removed near vias that contact the die. The final RDL connections to the die are generated by an auto-router after the true die locations are known.

In the case of adaptive patterning, the design rules specify the maximum die-shift for which the design can be adjusted. For both cases, a simple approach limits the die-shift to a range of X, Y, and θ values (e.g. −30 μm to 30 μm and -0.3°. The table below shows the magnitude of shift possible from rotation alone on several package sizes.

DECA 1

By adapting to die-shifts that are an order of magnitude larger than can be tolerated by traditional processes, this technology solves the last major industry challenge to adoption of fan-out packaging. The design rules for adaptive patterning are more complicated than traditional rules; however, this may be required for designs with high density interconnects and scarce routing space.

Siliconware – Fine Pitch RDL for High Density 2.5D

The original purpose of the Redistribution Layers (RDL) was to assist in the adaption of metal bumping and flip chip packaging technologies, by the addition of the metal and dielectric layers onto the wafer surface to re-route the legacy designed irregular peripheral I/O layout, into a new area array bond pads layout to facilitate a balanced metal bumps and flip chip bonding. The redistribution layer technology required polymeric thin film (e.g. BCB, Polyimide, PBO) as insulator and a semi-additive metallization scheme (often Cu pattern plating).

RDL technology, has extended its application into advanced packaging technologies, such as fan out wafer level packaging (FO WLP) and various TSV-less, substrate-less multiple chip integration, that to drive the cost effective miniaturization of system-in-package (SiP) application. The Cu RDL that in production, the line width/ spacing are 10 μm/10 μm or pitch of 20 μm .

The capability for fine pitch and multi layer RDL must be established at OSATs because the market is currently driving towards multiple chips integration and SiP applications. Furthermore, it is more difficult for the L/S < 2um due to there is no sufficient process window of lithography process.

While scaling from 10 to 3 μm poses no significant technical difficulties with existing tools, as long as the Cu thickness are proportional shrunk to keep the width/ height aspect ratio, below pitch of 6 μm, it is difficult to make such fine pitch layers on top of other layers, since the topography of multiple RDL with any planarization, that is out of the depth of focus (DoF) range of 2 μm and 1 μm, and such 2 μm / 4 μm pitches, would be limited to the first RDL in the multiple RDL scheme.

Cu dual damascene technology are generally used in ICs manufacturing or silicon interposer fabrication. CVD dielectric films (Si oxide, Si nitride) are commonly used in the modern IC fabrication fab (90nm and beyond), and can be used for up to three levels of 1um Cu RDL .

A comparison between a Cu dual damascene process and traditional organic RDL process are shown below. The Cu dual damascene process can provide a flat surface with excellent topography and we can combine this advantage with traditional RDL process to resolve the surface topography issue for the multiple RDL layers. For example in 3 layers RDL structure, we can use one dual damascene layer and two organic RDL layers to reduce the TTV of surface topography and then satisfy the DoF requirement of photo-resist materials.

SPIL 1

Cu dual damascene technology is a challenge for traditional bumping process and tools, especial for the lithography, Reactive-Ion Etching (RIE), Cu electroplating, and Chemical-Mechanical Planarization (CMP) steps. For the lithography process of Cu dual damascene, the key points are the opening dimension and profile of photoresist materials after the lithography process. Current development and research direction focus on the high resolution photo-resist materials and high numerical aperture (NA) exposure tools. The dielectric material of Cu dual damascene is generally silicon oxide (SiO2). In order to increase the oxide etching thickness accuracy, a thin silicon nitride (SiNx) film is deposited as stop layer between the oxide layers.

The figure below shows a silicon interposer structure with TSV and there are 3 dual damascene metal layers with u-pad in frond side of interposer and there is one RDL layer with C4 bumps on the backside of the interposer. The L/S are 1um and thickness 1um also for 3 dual damascene layers. And layers are connected by 0.5um diameter and 0.9um thickness via opening.

SPIL 2

Hybrid integration of the fine pitch CVD RDL with polymeric dielectric RDL is shown in the figure below. It is a substrate-less package with 0.4mm pitch BGA balls; the package size is 15mm x 14mm with one CVD dual damascene RDL with 2/2um line L/S combined with two organic RDL with 5/5um and 10/10um line L/S.

SPIL 3

 

The top die jointed with RDL by 40um pitch u-bump and molded by molded underfill (MUF) technology. The CVD oxide and nitride RDL 2/2um line L/S connected to organic RDL 5/5um line L/S by 10um via open which made by deep reactive-ion etching DRIE process. The second RDL contains 10/10um line L/S. This hybrid test vehicle passed open/short test after 96hrs of HAST, 1000 TCB cycles and 1000hrs of HTS.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 294 ECTC 2016: IMEC Discusses Economics of TSV Implementation Options

Tuesday, July 12th, 2016

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2016 IEEE ECTC conference.

IMEC – Economics of TSV Implementation Options

IMEC discussed their conclusions about the integration cost of TSVs for TSV middle vs TSV last processing. A 3D cost model developed at IMEC was used to analyze the cost of the different TSV integration approaches with different dimensions investigated for each flow.

IMEC 1

TSV lithography

The main difference in this step between the TSV middle and TSV last flow is that the TSV middle lithography is processed at a FEOL-fab compatible tool. In the case of TSV last an OSAT-fab compatible lower-cost tool can be used. This difference results in a TSV litho step cost which is approximately 30% more expensive for the TSV middle flow compared to TSV last flow. Furthermore, no difference on the lithography cost is observed due to different TSV dimensions.

Si TSV etch

The processing time for TSV etch depends on the TSV depth and the TSV aspect ratio. Smaller depth TSVs have faster etching times (for example the 5×50 vs. the 10×100 TSV process). In addition, TSVs with more aggressive aspect ratio have slower etching times (the 3×50 TSV middle compared to 5×50 or the 5×50 TSV last compared to 10×50).

TSV liner processing

Following the opening of the TSV hole in silicon, an insulating oxide liner layer is deposited. In the case of TSV middle, different liner deposition approaches are applied, depending on the aspect ratio of the via. In the case of an aspect ratio up to 1:10 a TEOS oxide is deposited. As the TSV aspect ratio becomes more aggressive (for 3×50 and 2×40 TSVs), a more conformal liner layer is required with higher uniformity in the liner thickness along the TSV. Therefore, a PEALD oxide deposition approach is preferred to achieve a liner thickness of 100nm, capped with 30nm SiN layer.

In the case of TSV last, the liner needs to be opened (etched) at the bottom of the via prior to further processing, therefore a highly conformal layer is required. For this reason a PE-ALD oxide deposition is used for all TSV geometries processed with the TSV last approach.

TSV liner opening (for TSV last flow) In the case of TSV last process flow, the oxide liner layer at the bottom of the TSV should be opened after deposition to allow for a conductive path towards the metal layers at the TSV bottom. This is one of the differentiating steps between the TSV middle and TSV last flows. Longer processing times (resulting in smaller tool throughput) are required for the narrower TSV diameter sizes.

TSV Barrier and Cu Seed processing

The first steps towards metallization of a TSV structure are the deposition of a barrier layer to prevent Cu diffusion, followed by a deposition of a Cu seed layer that will allow the Cu filling of the TSV through electroplating. Different deposition options are considered for different TSV sizes . In the case of TSV middle with aspect ratio 1:10 (i.e. 10×100 and 5×50), a PVD Ta barrier layer followed by a PVD Cu seed layer can be applied. As the TSV diameter is scaled further and the TSV aspect ratio becomes more aggressive, alternatives such as ALD processing are required. ALD deposition of 12nm TiN has been demonstrated as a successful barrier layer for a 3×50 TSV middle structure. The barrier and seed layers should be removed by CMP after the TSV processing flow. The cost of the CMP process depends on the thickness of the deposited layers. Therefore, the thin layers deposited by ALD can offer an advantage from a cost perspective when the processing cost of the CMP is also considered.

TSV Cu plating and impact on CMP

Plating time and material cost for the TSV filling depends upon the depth and the diameter of the TSV structure. TSV plating results in an overburden of Cu plated on top of the entire wafer area that needs to be removed by CMP. The Cu CMP process has two stages: (i) bulk Cu polish that is relatively fast and removes most of the plated Cu and (ii) fine Cu polish that is slower and clears the remaining Cu traces from the wafer surface, including the Cu seed layer.

Cost Comparison:

The overall processing flow cost can now be compared for different TSV geometries as shown in the figure below.

IMEC 2

In the case of the TSV last processing, the additional costs for the PE-ALD liner, etching the TSV liner within the via, and the backside CMP result in higher processing cost for the TSV last 5×50μm flow by up to 10%.

In the figure below it is demonstrated that scaling the TSV size and the TSV pitch is possible while keeping the processing cost under control. This is achieved by replacing the thicker PVD deposited layers used in the larger TSV geometries with thinner ALD layers for the scaled TSV sizes. Although the processing cost for the ALD layers is higher, the cost for CMP polishing of these thinner layers is lower. This tradeoff helps to control the processing cost as the size and pitch of TSV is scaled from 5×50 down to 3×50 and 2×40 TSV sizes.

IMEC 3

Overall it has been shown that main cost contributors for TSV processing are the CMP, the deep Si etch, and the barrier and seed deposition steps.

IMEC – Bumpless Process for 10µm Pitch Assembly

IMEC detailed the use of Damascene processing to achieve a bump-less assembly process for sub 10um pitch interconnects.

Microbumps and high density TSV pitches enable high density interconnects between two or more chip stacks for different applications. However, the mechanical stability of microbumps, bump height uniformity, microbumps under-cut during seed and barrier wet etching, high aspect ratio lithography process, dicing and handling issues and difficulty in thermo-compression bonding (TCB) alignment and stacking for fragile microbumps in 10um pitch range ae serious concerns.

In the IMEC bumpless process UBM in the bottom die is embedded in BEOL dielectric and is fabricated in by damascene processing enabling less bump height variation, smooth UBM surface and thus pitch reduction. Schematic of the bump-less process concept is shown below. The top die which contains UBM and solder, the UBM is plated in dielectric followed by Sn plating in resist. After stripping resist and seed/barrier wet etching, polymer (CA6001B from Hitachi ) is coated and planarized by CMP or surface planer. After Sn plating and seed etch, microbumps were embedded in a spin coated polymer followed by a soft bake step. For planarization, CMP and surface planer tools were used. Polymer acts as support material for planarization and also as underfill material for 3D stacking.

IMEC 4

During fast TCB bonding, the polymer starts to reflow and bond to the oxide followed by Sn / Cu reaction and IMC formation and final polymer cure.

Processing is on-going in IMEC with 5um pitch TSV and bump for die to die, die to wafer and wafer to wafer bonding applications.

For all the latest on 3DIC and other advanced packaging applications, stay linked to IFTLE…

IFTLE 293 Sarda Voltage Regulators; ECTC 2016 – Copper Pumping; Copper Pillar on Embedded Trace

Tuesday, July 5th, 2016

By Dr. Phil Garrou, Contributing Editor

Sarda Heterogeneously Integrated Power Stage

Sarda, UTAC and AT&S announced at the recent Int Symp on 3D Power Electronics, Integration and Manufacturing Symposium that they would be using UTAC’s “3D SiP” technology (based on ECP technology from AT&S) to deliver small, fast voltage regulators for use in data centers.

Sarda’s Heterogeneous Integrated Power Stage (HIPS) technology replaces Si switches with GaAs switches in voltage regulators which reportedly increases switching frequency by 10X, improves transient response by 5X and reduces size by 80%. This in turn can reportedly reduce data center power consumption by 30%.

Sarda

Continuing our look at the 2016 ECC presentations:

 

Osaka Fine Feature Electrodeposition Res Center – Copper Pumping

Kondo from the Fine Feature Electrodeposition Research Center in Osaka discussed his solutions for copper pumping. We have known for years that the use of silicon vias (TSVs) causes copper extrusion during copper annealing due to the mismatch of the thermal expansion coefficient of Cu and Si. This extrusion can cause damage to the interconnect above it, as shown in the figure below.

Beyne and co-workers at IMEC developed a solution for avoiding this damage by annealing the TSV at >425 °C and then CMP’ing the resultant copper protrusions before building the layers of on chip interconnect.

Kondo 1

The Small Feature Electrodeposition Lab has now reportedly developed an additive “A”, which restricts the copper pumping phenomena and thus eliminates the need for CMP. A comparison of pumping with and without additive A at 450°C is shown below.

Kondo 2 Pumping at 450°C (a) room temp; (b) without additive “A” at 450°C ; (c) room temp ; (d) without additive “A” at 450°C

 

The resistivity of electrodeposited copper TSV after 450℃ annealing for the wiring is only 1.09x that of conventional electrodeposited copper.

Initial investigations of the mechanism of this reaction point to 100nm carbon deposition into the triple point of the copper grains which causes unit cell contraction upon annealing .

Amkor – Copper Pillar on Embedded Trace

The continuing push toward miniaturization in both planar & stack-up dimensions, has driven the use of chip-scale packages (CSP) in consumer microelectronics.

The state of the art method for joining die and substrate is currently using solder-capped copper pillars. The pillar and solder are previously plated onto the die through wafer level processing. The advantages of copper pillar technology have been well documented and include greater reliability by inhibiting electromigration , as well as enabling fine pitch interconnects.

There have also been advances on the substrate side where thinner packages are the goal. One

enabling technology has been the development and use of Embedded Trace Substrates (ETS), where the top-layer metal is embedded into the dielectric material instead of being deposited on top of it. This results in a near-planarity of the dielectric material and the top-layer of metal as shown in the figure below.

amkor 1

The advantages of ETS include a lower profile, potential layer reduction and reportedly lower cost. Substrate manufacturing costs and stack-up height are both reduced due to the absence of a core material. Layer reduction can take place due to removal of restrictive core-layer design rules.

Warpage is a real concern in the assembly of packages with ETS, but for applications where warpage can be properly managed, the combination of copper pillar bonding on ETS offers low-cost, thin solutions for packaging advanced devices.

While the near-planarity of metal traces with the surface of the substrate in ETS is effective at reducing the risk of bump-to-trace shorting, there is a corresponding increase in the risk of electrical opens especially as L/S shrinks. Amkor has developed a model to test for interconnection reliability between copper pillar bumps and ETS bond pads, based on design parameters and in-process variables. The critical recess depth of the ETS bond pad is identified as a key parameter linked to interconnection success. Reducing the risk of non-wets requires attention to design and processing during substrate manufacturing, bumping, and assembly.

For all the latest on 3DIC and other advanced packaging stay linked to IFTLE…