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IFTLE 292 New Fab Construction? Look to China; Rumors from ECTC: InFO — ASE — DECA

By Dr. Phil Garrou, Contributing Editor

Fab Construction Declining, New Construction be mainly in China.

Over the last few years, IFTLE has detailed the slowdown in scaling which is leading to the construction of fewer and fewer latest node fabs. We have also noted that this maturity of our industry has led to the consolidation trend that has been so prevalent the past few years.

Peter Clarke of EE Times Europe recently reported the latest SEMI data on new fab construction [link]. They predict 19 wafer fab starts in 2016 and 2017 and predict that China, will be responsible for more than half of them. This is a low total number by historical standards consistent with our trend of slowdown.

(12) of the fabs are 300mm, (4) are 200mm, and the (3) LED fabs are 150mm, 100mm, and 50mm respectively. Activity in the 3D NAND, 10nm logic, and foundry segments is expected to push equipment spending up 1.5% globally vs 2015. Fab equipment spending declined by 2 percent in 2015. SEMI lists a probability 60% or higher for these predictions but admits that some may be delayed.

fabs 1

The heavy participation by China is also consistent with IFLE noting that China would be the Wild card when it comes to future IC production (see “IFTLE 238 ASE & the Apple watch, ASE / TDK JV; China: the Wild Card” [link]).

SEMI estimates far more manufacturers are looking at fab upgrades or facility conversions as shown in the table below. IFTLE agrees that this is likely the way of the future.

fab 2

Continuing our look at the 2016 ECTC

Wafer Level Integrated Fan Out Packaging (InFO) – TSMC


IFTLE has stated over and over that the front end practitioners are paying more and more attention to packaging because they understand that it is the future way of customizing a circuit and could have more value in the long run than further scaling. (At least till the CMOS replacement is found sometime in the future). This was never made clearer than by the rumors that TSMC had been selected as Apple’s exclusive manufacturer for this year’s A10 chip expected to power the iPhone 7 and new iPad models. “The new chip is expected to use a 16nm process combined with a new InFO packaging, which allows chips to be stacked on top of each other and mounted directly to a circuit board, instead of onto a substrate first, reducing both the thickness and the weight of devices. Apple is rumored to be TSMC’s first customer to use InFo.”[link]

In fact it is likely that this was also a main motivation for Samsung EM’s recent announcement that they would be entering the FO-WLP business by the end of the year.( see IFTLE 291 : “Samsung EM enters FO-WLP Packaging Mkt…” [link] ).

Session 1 paper 1 at the 2016 ECTC was a TSMC paper on InFO by Doug Yu and his team at TSMC. Up until a few years ago, Doug had been the key technology Mgr developing the latest front end copper low K interconnect for each succeeding scaling generation at TSMC. He now runs 2.5D and wafer level packaging like InFO…does that tell you anything ? I think it does.

Since they first indicated that InFO was on their radar , ~ 2012, TSMC has focused on presenting comparative data showing the better performance that InFO would deliver vs other options. This latest paper continues in that venue comparing the form factor and performance advantages of InFO PoP over std FC-PoP. What’s been missing from the InFO presentations has been any detail on the process flow. (see IFTLE 261: “….The info on InFO…” [link].

In IFTLE 261, we reported on a rumored InFO process flow which consists of (1)copper pillar plating on the die,(2) die placed face up on tape, (3)molding to generate reconstituted wafer, (4) polish down to reveal tops of pillars, (5) RDL processing on this polished surface. The capability for finer features than standard fan out packaging comes from the more planar starting surfaces and better control of the photo processes.

A prevalent rumor going around ECTC is that ASE will become the second source of InFO technology for the industry. Does this make sense ? Well ASE is known to be a preferred partner for TSMC packaging and ASE has won its own Apple contracts for supplying SiP for the Apple watch (see IFTLE 238: “ASE & the Apple watch…” [link]). So yes I’d say this is plausible.

In addition ASE and DECA have just announced that ASE has licensed the DECA FO technology and will be putting in a line to manufacture it. [link]

Is it logical that ASE is about to scale up two different fan out packages at the same time ?…..probably not.

It is more logical if the TSMC process and the DECA process are similar enough that this really constitutes only ONE line for both products.

The DECA process flow (as published in the 2013 IWLPC) is shown below.

DECA DECA Process Flow

Enough said…

For all the latest on 3DIC and advanced packaging stay linked to IFTLE…

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