IFTLE 281 ASE Takeover of SPIL Halted But Not Stopped; After Silicon Scaling Comes…
By Dr. Phil Garrou, Contributing Editor
The Taipei Times is reporting that the Taiwan Fair Trade Commission has suspended its review of ASE’s bid to take over SPIL (link). ASE’s prior acquisition of a 25% stake in SPIL has raised anti-trust concerns and fears that the merger would undermine competition in the market.
The decision means a victory for SPIL who has fought the acquisition. SPIL, which has repeatedly urged the commission to terminate the review of the acquisition welcomed the FTC’s decision.
ASE released a statement saying it will continue with our plan to acquire 100 percent equity interest in SPIL through all legally permissible means and avenues.” ASE will be able to continue raising its ownership in SPIL through open market purchases including intra-day trading, block trades, and acquisition of SPIL’s Nasdaq-listed American depositary receipts. If ASE’s stake in SPIL exceeds the 33% threshold, ASE will need to apply to Taiwan’s Fair Trade Commission (FTC) to merge with SPIL.
Intel Admits Moore’s Law Coming to an End…Predict What Might be Next
The recent issue of MIT technology review noted that “Intel will slow the pace at which it rolls out new chip-making technology, and is searching for the appropriate successor to silicon transistors.” (link)
They note that Intel in their 2015 10K report last month disclosed that it is slowing the timing at which it moves to the next scaling node. Intel has already pushed back the debut of its first 10nm chips from the end of this year to sometime in 2017 noting that it can’t keep up the pace it used to.
We all know it is becoming more difficult to shrink features further in a cost-effective manner, but this doesn’t mean that future devices will stop improving. Intel says that in the future, it will make improvements to the way chips are designed. They add that for many important new applications such as wearable devices and medical implants, chips are already powerful enough and power consumption is more important.
William Holt, who leads the company’s technology and manufacturing group, speaking at the International Solid State Circuits Conference said that for chips to keep improving, Intel will soon have to start using fundamentally new technologies in about four years. While Intel has not yet announced silicon’s successor, most technologists feel that the two leading candidates are spintronics and tunneling transistors.
Neither of these technologies offer increases in computing power and neither are ready for volume manufacturing. Both would require major changes in how chips are designed and manufactured. While neither offer speed benefits over silicon transistors, the new technologies would, improve energy efficiency something important for many leading uses of computing today, such as cloud computing, mobile devices, and robotics. Future chips connect to household, commercial, and industrial objects and thus will need to be as energy efficient as possible.
Sine packaging experts need to be aware of what’s going on in the front end lets take a look at these technologies.
Conventional electronic devices rely on the transport of electrical charge carriers – electrons – in a semiconductor such as silicon. Spintronics or “spin transport electronics”( also known as magnetoelectronics), depends on the intrinsic spin of electrons and the associated magnetic moment, in addition to its fundamental electronic charge, in solid-state devices. Devices follow the simple sequence:
1 – information is stored (written) into spins as a particular spin orientation (up or down),
2 – the spins, being attached to mobile electrons, carry the information along a wire, and
3- the information is read at a terminal.
Spin orientation of conduction electrons survives for a relatively long time which makes spintronic devices particularly attractive for memory storage and magnetic sensors applications, and, potentially for quantum computing [link].
The basic TFET structure is similar to a MOSFET except that the source and drain terminals of a TFET are doped of opposite type. A common TFET device structure consists of a P-I-N (junction, in which the electrostatic potential of the intrinsic region is controlled by a gate terminal. The device is operated by applying gate bias so that electron accumulation occurs in the intrinsic region. At sufficient gate bias, tunneling occurs when the conduction band of the intrinsic region aligns with the valence band of the P region. Electrons from the valence band of the p-type region tunnel into the conduction band of the intrinsic region and current can flow across the device. As the gate bias is reduced, the bands becomes misaligned and current can no longer flow.
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