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IFTLE 279 2016 European 3D Summit: Cost Modeling Memory Stacks; Needed Tech for Next Gen 3DIC

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the key presentations from the 2016 SEMI European 3D Summit that took place in January.

System Plus Consulting

System Plus Consulting showed an interesting cost comparison between AMD graphics modules with DDR5 vs HBM memory as shown below.

Sys plus 1

Also of interest is their look at the supply chain for the new AMD 2.5D module. ASE is assembling die from TSMC and Hynix on a UMC silicon interposer and mounting on an Ibiden substrate.

sys plus 2

Also of interest is their assessment of the Hynix HBM process cost.

sys plus 3

 

The Samsung 4 GB DDR4 DRAM stacks consist of 7um TSV on 67um pitch with 33um ubumps. The process uses thermocompression bonding, wafer level NCF underfill and Suss temporary bonding with Nissan (formerly TMAT) silicone underfill.

sys plus 4

IMEC

Eric Beyne who has been active in 3DIC since its early beginnings focused on technologies that will be important for 3DIC to further penetrate the electronics industry. Beyne started out with a look at where 3D TSV technology sits as we enter 2016, namely interposers, FPGAs, graphics modules and memory stacks (shown below)

imec 1

 

Beyne sees the TSV themselves continuing to shrink going from the standard 5 x 50um a few years ago to a 2 x 40um in the near future. This has required changes in Cu barrier layer and Cu seed dep as shown below.

IMEC 2

 

He proposed the following IMEC ubump strategy:

imec 3

 

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

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