Part of the  

Solid State Technology

  Network

About  |  Contact

Archive for March, 2016

IFTLE 280 2016 European 3D Summit: Economic Profit in Today’s Micro electronics

Monday, March 28th, 2016

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2016 SEMI European 3D Summit.

McKinsey

A very interesting chart from McKinsey on 2014 economic profit in the microelectronics industry (below). It is clear that very few companies are responsible for most of the economic profit.

McKinsey 1

The big 5 of Intel, TSMC, Qualcomm, TI and Samsung contributed > 70% of the entire industries economic profit for the last 15 years.

The following are the top 10 2014 assembly and test companies.

mckinsey 2

While market share is key in most semiconductor industry segments, there is no such link in assembly and test. Partnerships and portfolio appear to be the most important factors I assembly & test.

Their key trends for Assembly & test are:

mckinsey 3

None of these should be a surprise to readers of IFTLE.

Fraunhoffer Inst

In a joint presentation by the different Fraunhoffer Institutes in Germany, Andy Heinig show the following comparison of their SiO2 and polymer based processes.

Fraunhoffer 1

They indicate that the required number of routing layers not only depending on component complexity (i.e., pin count, pitch), but also on interposer material composition ( i.e. polymer vs SiO2 based)

- Polymer-based interposers with increased width and spacing of interconnect require a minimum of 3 metal layers

- Finer L/S of SiO2-based interposers allows routing on a single metallization layer

- Different consideration for power/ground nets (larger line/space) necessary

3M

The 3M wafer support system for thinning and backside processing has been around for several years. Their standard process is shown below.

3M 1

They are also developing a thermal cure adhesive that can be mechanically debonded. This eliminates the LTHC layer and the laser module. Properties are shown below.

3M 2

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

 

IFTLE 279 2016 European 3D Summit: Cost Modeling Memory Stacks; Needed Tech for Next Gen 3DIC

Wednesday, March 23rd, 2016

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the key presentations from the 2016 SEMI European 3D Summit that took place in January.

System Plus Consulting

System Plus Consulting showed an interesting cost comparison between AMD graphics modules with DDR5 vs HBM memory as shown below.

Sys plus 1

Also of interest is their look at the supply chain for the new AMD 2.5D module. ASE is assembling die from TSMC and Hynix on a UMC silicon interposer and mounting on an Ibiden substrate.

sys plus 2

Also of interest is their assessment of the Hynix HBM process cost.

sys plus 3

 

The Samsung 4 GB DDR4 DRAM stacks consist of 7um TSV on 67um pitch with 33um ubumps. The process uses thermocompression bonding, wafer level NCF underfill and Suss temporary bonding with Nissan (formerly TMAT) silicone underfill.

sys plus 4

IMEC

Eric Beyne who has been active in 3DIC since its early beginnings focused on technologies that will be important for 3DIC to further penetrate the electronics industry. Beyne started out with a look at where 3D TSV technology sits as we enter 2016, namely interposers, FPGAs, graphics modules and memory stacks (shown below)

imec 1

 

Beyne sees the TSV themselves continuing to shrink going from the standard 5 x 50um a few years ago to a 2 x 40um in the near future. This has required changes in Cu barrier layer and Cu seed dep as shown below.

IMEC 2

 

He proposed the following IMEC ubump strategy:

imec 3

 

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 278 Omnivision Stacked CIS; Apple Fingerprint Sensor with TSV

Tuesday, March 15th, 2016

By Dr. Phil Garrou, Contributing Editor

Sony Samsung and Omnivision are locked in a technology battle for superiority in CMOS image sensors. While Sony has the lead in stacking technology, i.e. stacking the sensor on top of the image processor and connecting them with TSVs, OmniVision and Samsung quickly adopted the same technology and gained design wins using stacked chip products.

Rumor is that Sony will be working with GlobalFoundries on chip stack CIS, instead of Samsung to avoid any conflict with Samsung who is also in the CIS business.

We recently updated the latest from Sony [see IFTLE 272] Now lets look at some of the latest activity from Omnivision and Samsung.

Omnivision CIS

We last looked in depth at Omnivision in IFTLE 199 [ see IFTLE 199 Omnivision Roadmaps 3D stacking for CMOS Image Sensors…”]

The Omnivision OV13860 introduced in late 2014 is a 13 MP back side illuminated sensor with 1.3um pixels (actually larger than other 13MP sensors). It is the first Omnivision’s CIS built with stacked die technology which separates the imaging array from the image sensor processing circuits in the stacked structure. This allows for more functionality to be incorporated on the sensor die while resulting in a smaller size due to the stacking. [link].

Omnivision then announced the OV16850, a 16MP imager for smartphones. Using an 1.12um pixel and leveraging OmniVision’s stacked die technology, which captures stills and video in native 16:9 aspect ratio. This was followed by the OV23850 a 23.8 MP high resolution CIS. (images below [link]

Omnivision Credit: Chipworks Omnivision Xsect Credit: Chipworks

Samsung

Samsung’s first entrant into stacked technology with TSV was also at 16MP with the Samsung S5K3P3SX in late 2014. The CIS die is face-to-face bonded to a 65nm Samsung image signal processor die and connected with W based TSV. The CIS die is fabricated on a 65nm CMOS process with 5 levels of interconnect as shown below. [link]

Samsung 16 MP Credit: Chipworks Samsing Xsect Credit: Chipworks

iPhone 6s Plus Fingerprint Sensor

The Apple iPhone 6s now has a “touch ID” fingerprint sensor embedded in the Home button.

While it is now used for unlocking the phone , it will also be used for identification purposes for Apple Pay mobile payments. It will also probably be used for other online services in the future.

The new device has the same structure and capacitive technology as the previous one, but with changes in sensor design and packaging.

The 12.5×10.9mm sensor is incorporated within a rectangular shaped housing composed of a stainless steel ring and an aluminum base. The sensor is protected by a sapphire window coated with two different materials and supported by innovative assembly of dies and flex PCB. The finger print sensor allows it to scan the fingerprint just by pushing the button. The sensor has a resolution of 10,752 pixels with a pixel density of 500ppi. It uses a capacitive touch technology to take an image of the fingerprint from the sub epidermal layers of the skin.

Apple FP

The new sensor has two die, a sensing die manufactured with 65nm CMOS technology and an 0.18um ASIC logic die. The new sensor is implemented with TSV (shown below) which allows a better packaging and connection to the flex connector.

Apple finger print TSV

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 277 SEMI ISS 2016 Part 2: Scaling Under Pressure; Tsinghua Bets on Packaging

Tuesday, March 8th, 2016

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the SEMI 2016 ISS meeting.

Pacific Crest

Daniel Bakshet of Pacific Crest Securities pointed to the following changes in the semiconductor industry:

- economics are becoming challenged as process complexity increases

- compute functions are shifting from local to the cloud

- PC, tablet and smartphone demand is decelerating or declining

- signs of maturation are emerging as M&A becomes a dominant theme

They use the figure below to make the point (as we have for several years in IFTLE) that moving to a lower node no longer results in lower costs.

pacific crest 1

They see less demand for advancements in local compute capability as more of the compute function is conducted in the cloud.

They project that device growth is more likely to come from lower end products and thus not likely to require leading edge chips. They actually predict a reasonably good chance that incremental wafer demand declines at the leading edge, while previous nodes thrive.

They see autonomous Vehicles and Robotics as the areas of future growth.

Micron

Micron’s presentation by Mike Sadler, VP of corporate Development focused on consolidation in the memory industry with the following interesting slide showing acquisition and partnership driven capacity growth at Micron.

micron 1

Gartner

Bob Johnson of Gartner showed this nice summary of when the remaining players have announced that they will continue scaling.

Gartner 1

 

SMIC

Sonny Hui of SMIC showed the following figure of the % of devices manufactured (assembled) in China.

SMIC

Amkor

Ron Huemoeller focused on Amkors high density SWIFT and SLIM packaging which we have detailed previously [see IFTLE 243 Amkor Fan Out Package Platforms] with the following product positioning slide and the following expected timeline.

Amkor 1

Amkor 2

China’s Tsinghua group looking to buy into Global Packaging Industry

Reuters recently discussed the offers to acquire 25% stakes in ChipMos, PowrChip and SPIL by the Tsinghua group in China. [link]

The Chinese state-backed conglomerate aims to buy into the island’s technology sector as a step toward building China’s own semiconductor industry. Tsinghua made offers in quick succession late last year for a quarter each of chip testing and packaging companies Powertech Technology Inc, ChipMOS Technologies Inc and Siliconware Precision Industries Co Ltd (SPIL). The company plans to inject a total of $2.6 billion into the three in exchange for stakes plus one board seat at each with no management control. The offers came after Micron Technology Inc rejected Tsinghua’s informal $23 billion takeover bid on the presumption of U.S. national security concerns.

Shareholders of Powertech and ChipMOS approved the plans in January as they seek capital to expand and survive in a global chip sector experiencing record merger and acquisition activity.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 276 SEMI ISS 2016: The Focus Shifts to Packaging

Wednesday, March 2nd, 2016

By Dr. Phil Garrou, Contributing Editor

The annual SEMI ISS (Industry Strategy symposium) meeting took place as usual in January in Half Moon Bay CA. What was different was something that IFTLE has been predicting for while: “In the future when the front end community runs out of advances they will begin to focus on assembly/packaging.” Well…the future is NOW.

Intel

Intel’s Corporate VP Babak Sabi got on the packaging bandwagon with his presentation “Maintaining the IC Scaling Edge through Packaging.”

He showed the following detail on their Altera FPGA demonstrator using their Intel EMIB technology [for technology detail see IFTLE 209 “Samsung announces TSV based DDR4; What is Intel eMIB?”]

Intel 1

The following is an interesting comparison of Intel’s understanding of feature size vs substrate technology.

Intel 2

Qualcomm

Mike Campbell of Qualcomm focused on “module and 3D packaging as the new integration path for semiconductors.”

Showing the following example for future SiP heterogeneous integration in a 2.5D format and the required enabling technologies.

qualcomm 1

SEMI

Dan Tracy – Dir of SEMIs Industry research group also focused in packaging in his presentation “It’s All About Packaging—In this Materials World That We are Dealing With” using materials supplied by TechSearch Inc.

Looking first at materials supplier consolidation:semi 1

Mobil products are certainly the driver for packaging.

semi 2

He offered the following comments for individual markets:

Mold Compounds

- $1.2B market size

- stable Japanese supply base

- focus on warpage control, CTE, low moisture, low ionics

- molded underfill (MUF) for CU pillar FC

- high TC and high V apps emerging

Underfill

- global mkt $250MM

- currently 30+ suppliers [note from IFTLE so this is ripe for consolidation]

- new resins and fillers for fine pitch requirements

- No flow applied prior to chip placement – both liquid and film based

- use of mold compound as underfill

- increased use of board level underfill for CSP, BGA, WLPs

Wafer Level Dielectrics

- $90MM market

- requirements for new material entrants include – low temp cure, low warpage

IBS

Handle Jones of IBS presented the following projection for wafer level packaging which he claims is being driven by Apple. Note he projects that we will be approaching 1MM WLP wafers/month by 2020.

IBS 1

Jones also noted that with the acquisition of STATSChipPAC, JCET has become the worlds 3rd largest OSAT.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…