IFTLE 274 3D ASIP 2015 Part 4: Comparing Memory Architectures; On the Passing of Moore’s Law
By Dr. Phil Garrou, Contributing Editor
Continuing our look at the 2015 3D ASIP conference, one of the themes of this years conference was the coming of age of 3D stacked memory which now comes in several flavors from several vendors. This week, we’ll look at the Yole review and next week finish off with a look at the presentations by Toshiba, Hynix, Micron, AMD and Tezzaron.
In the plenary presentation, Thibault Buisson of Yole spoke on the “Comparison of new Memory Architecture -3D TSV Memory Packaging trends!” Some of the recent product and technology announcements are shown below. After MEMS and CIS, stacked Memory has become the next segment to see adoption of TSV technology. Graphics has been the first application using 3D stacked memories.
All of the major memory suppliers ow have TSV based memory stacked products.
Yole estimates that the SK Hynix HBM stack price with an assumption of 50% gross margin will range from $12.68 to $18.01 per stack.
They further conjecture that the AMD Radeon pricing rages from $191 to $258 with the GPU dies represening 43% of the component cost; the (4) HBM stack representing 28% , the silicon interposer representing 14% and the package subsrate 12%
Toshiba has announced the world’s first NAND flash memory packages integrating (16) 128 Gb NAND memory devices connected together using TSV. The multi-layer chips feature 1Gb/s data rate, 1.8V core voltage and 1.2V I/O voltage. The new packages use 50% less energy on write operations, read operations, and I/O data transfers than Toshiba’s current memory products. (see more below)
The stacked memory supply chain is also clarifying.
- The HBM stack (memory dies, logic die) is made by Memory Manufacturer
- The GPU die is manufactured by wafer foundry
- The interposer is also manufactured by wafer foundry (could be a different one compare to GPU)
- The PCB package substrate is made by a substrate manufacturer
- The final assembly (HBM, GPU, interposer, interposer on PCB, passives assembly and BGA balls) is performed by an OSAT.
X-sect comparison of Hynix HBM to Samsung stacked DDR4 is shown below.
On the Passing of Moore’s Law
Every once in awhile you find an article and say “this is great, this is exactly as I would have written it”
I recently found such an article on the passing of Moore’s Law …or…as the author Peter Bright states it
“…Moore’s Law has passed away at the age of 51 after an extended illness” [link]
I hate to take up space just quoting him, but as I said I couldn’t have written it any better, so…
“In the 2000s, it [became] clear that … geometric scaling was at an end, but various technical measures were devised to keep up the pace of Moore’s law…. At 90nm, strained silicon was introduced; at 45nm, new materials to increase the capacitance of each transistor layered on the silicon were introduced. At 22nm, tri-gate transistors maintained the scaling.
Even with EUV, it’s unclear just how much further scaling is even possible; at 2nm, transistors would be just 10 atoms wide, and it’s unlikely that they’d operate reliably…as the transistors are packed ever tighter, dissipating the energy that they use becomes ever harder.
The new techniques, such as strained silicon and tri-gate transistors, took more than a decade to put in production. EUV has been talked about for longer still. There’s also a significant cost factor. Technology may provide ways to further increase the number of transistors packed into a chip, but the manufacturing facilities to build these chips may be prohibitively expensive.
Compounding all this is that all these extra transistors have become increasingly hard to use. In the 1980s and 1990s the value of the extra transistors was obvious: the Pentium was much faster than the 486, the Pentium II much faster than the Pentium. Those easy improvements stopped coming in the 2000s. Constrained by heat, clock speeds have largely stood still, and the performance of each individual processor core has increased only incrementally. What we see instead are multiple processor cores within a single chip. This increases the overall theoretical performance of a processor, but it can be difficult to actually exploit this improvement in software.
These difficulties mean that the Moore’s law-driven roadmap is now at an end. ITRS decided in 2014 that its next roadmap would no longer be beholden to Moore’s “law,” and… the next ITRS roadmap, published next month, will take an approach it describes as “More than Moore.”
IFTLE is in full agreement, as you know IFTLE thinks technologies like 2.5 and 3DIC have replaced Moore’s Law. May Moore’s Law rest-in-peace…
Those who continue to preach that “Moore’s Law is still alive and well” are akin to those who claim to have seen Elvis yesterday on the streets of Nashville!
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