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IFTLE 267 The 2015 IWLPC: DECA, SPTS, IMEC / KLA-Tencor, IMEC / EVG

By Dr. Phil Garrou, Contributing Editor

This week, let’s take a quick look at the 12th annual Int. Wafer Level Packaging Conference (IWLPC) which was held in San Jose in October. But before we do, a Christmas message from my granddaughters:

H&M

IWLPC 2015

The 2015 IWLPC technical focus consisted of   1) fan-out WLCSP, 2) 2.5 and 3D IC packaging, and 3) MEMS. This conference is becoming a major player in the exhibition end of the packaging business this year having 65 booths set up in San Jose.

IWLPC

DECA

We have looked at the activity of Deca several times since their initial pronouncements in 2012 [see IFTLE 124, “Status and the Future of eWLB; Will Deca lower the cost of FO-WLP” and IFTLE 175, “2013 IWLPC; 450mm on Hold?”]

Cost, yield and reliability issues have effectively limited the widespread adoption of FOWLP. Placing singulated chips on the carrier to form the molded panel requires high placement accuracy. Any misplacements can lead to pattern overlay difficulties in the buildup process on the reconstituted panel. The requirement for high placement accuracy restricts throughput at the pick-and-place operation, leading to high process costs. During the molding operation and mold cure, die drift or movement can occur. This die drift can further complicate pattern overlay matching in the buildup process on the panel and can result in yield loss when the drift is excessive.

In the DECA process die with preformed Cu studs are placed face-up on a carrier, using a high speed pick and place tool. The front and sides of the die are then covered with mold compound using compression molding. The molded panel is debonded from the carrier, and the front surface is ground to reveal the Cu studs. A high speed optical scanner is used to determine the actual position of every die on the panel. This information is fed into a proprietary Adaptive Patterning design tool, which adjusts the fan-out unit design for each package on the panel to match actual die locations. Finally, the design files for each panel are imported to a lithography machine which uses the design data to dynamically apply a custom, Adaptive Pattern to each panel during the fan-out build-up process. Adaptive Patterning works by dynamically adjusting one or more build-up layers to accurately connect to the Cu studs protruding through the mold compound for each individual die in the molded panel.

After the Adaptive Patterning design files are created, fan-out processing can commence. The build-up proceeds through polymer 1, RDL, polymer 2 and UBM layers, with the lithography system implementing unique designs at the polymer 1 and RDL layers on a per panel basis. Finally, ball attach and package finishing are performed to produce singulated fan-out packages.

deca 1

The board level reliability was examined for a 8mm X 8mm package with 324 IOs on a 0.4mm pitch. The packages were mounted to 1mm thick printed circuit boards (PCBs) with non-solder-mask defined PCB pads. Standard JEDEC conditions were used for temperature cycling and drop testing. First cycling failure occurred at 665 cycles and with no failures observed up to 250 drops.

SPTS – Plasma Dicing

Plasma dicing is attracting significant interest within the semiconductor industry as a viable alternative to conventional singulation methods using saw blades or lasers. Plasma dicing promises benefits such as increasing wafer throughput, die per wafer and die yields (due to low damage processing). For small die, in particular, where the time required for a high number of mechanical slices in “series” can be substantial, a “parallel” process such as plasma dicing which etches all dicing lanes simultaneously, can significantly increase wafer throughput.

Maximum benefits are gained when plasma dicing is “designed in” from the beginning. With dicing lanes defined by photolithography, these lanes can be narrower than the width of a dicing blade, saving valuable silicon real-estate which can be used to increase the number of die per wafer. Also, the designer can make sure that dicing lanes are free from metals and other layers which can hinder plasma etching. This is often quoted as the prime challenge which prevents implementing plasma dicing in an existing production scheme.

IMEC / KLA Tencor

IMEC / KLA Tencor shared their results on investigations to determine the best way to insure µbump presence and co-planarity. µbump dimensions are being scaled down to 20 um pitch (10 µm in width and 8 µm high). For die-to-die and die-to-wafer stacking, the need for highly accurate and repeatable measurement of µbumps at both die-level and wafer-level is a must for this technology to become a viable industrial option.

Bump co-planarity is defined as the difference between the heights of the tallest and the shortest µbump within a die as shown below.

IMEC 1

A failure to properly characterize the co-planarity of each die and detect defects of interest such as damaged, missing or mislocated bumps can lead to the wrongful classification of the die as suitable for asembly. This may have a number of yield-affecting consequences during stacking, such as open and short circuits, die cracking and thermal sinks. As the number of die in a typical die stack increases, a single falsely classified die will affect the entire product.

One of the challenges in constituting a meaningful subset for measurement is to define a population of µbumps which is large enough to be statistically significant and to select µbumps from areas in the die which will represent height range and coplanarity of the full die.

Nanium / EVG

Nanium and EVG shared some information on Temporary Wafer Carrier Solutions for Thin FOWLP and eWLB-based PoP.

In order to achieve a cost competitive position related with other packaging technologies, FOWLP has been using 300mm diameter reconstituted wafers, which brings challenges related with its mechanical and thermomechanical properties like wafer bow, wafer warpage and wafer expansion. Nowadays, more FOWLP designs require reconstituted wafers with thickness below 400um. When wafer thickness drops below 400~450um, the reconstituted wafers acquires a flexible behavior that does not allow self-supporting handling anymore.

Adding to this challenge, the need for RDL processing on both sides of the eWLB wafer, for 3D and PoP constructions, requires the temporary protection of one RDL side while the other is being built. Solutions such as temporary wafer bonding for 2.5/3DIC technology , cannot be copied-exact for eWLB wafers because of the very high and non-linear thermomechanical behavior of such wafers and to the temperature limitations the molded material imposes. For example, Si wafers failed as carriers due to the mechanical mismatch to eWLB wafers and with adhesives with bonding process temperature above 200ºC . The selection of carrier wafer and adhesive material are key elements to the success of any temporary bonding and debonding technique for eWLB or fan out in general.

Based on their studies we are not told what the preferred carrier or temp adhesive are, but we are led through several solutions and told what properties lead to the best results.

For all the latest on 3DIC and other advanced packaging options, stay linked to IFTLE…

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