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Archive for December, 2015

IFTLE 267 The 2015 IWLPC: DECA, SPTS, IMEC / KLA-Tencor, IMEC / EVG

Tuesday, December 22nd, 2015

By Dr. Phil Garrou, Contributing Editor

This week, let’s take a quick look at the 12th annual Int. Wafer Level Packaging Conference (IWLPC) which was held in San Jose in October. But before we do, a Christmas message from my granddaughters:

H&M

IWLPC 2015

The 2015 IWLPC technical focus consisted of   1) fan-out WLCSP, 2) 2.5 and 3D IC packaging, and 3) MEMS. This conference is becoming a major player in the exhibition end of the packaging business this year having 65 booths set up in San Jose.

IWLPC

DECA

We have looked at the activity of Deca several times since their initial pronouncements in 2012 [see IFTLE 124, “Status and the Future of eWLB; Will Deca lower the cost of FO-WLP” and IFTLE 175, “2013 IWLPC; 450mm on Hold?”]

Cost, yield and reliability issues have effectively limited the widespread adoption of FOWLP. Placing singulated chips on the carrier to form the molded panel requires high placement accuracy. Any misplacements can lead to pattern overlay difficulties in the buildup process on the reconstituted panel. The requirement for high placement accuracy restricts throughput at the pick-and-place operation, leading to high process costs. During the molding operation and mold cure, die drift or movement can occur. This die drift can further complicate pattern overlay matching in the buildup process on the panel and can result in yield loss when the drift is excessive.

In the DECA process die with preformed Cu studs are placed face-up on a carrier, using a high speed pick and place tool. The front and sides of the die are then covered with mold compound using compression molding. The molded panel is debonded from the carrier, and the front surface is ground to reveal the Cu studs. A high speed optical scanner is used to determine the actual position of every die on the panel. This information is fed into a proprietary Adaptive Patterning design tool, which adjusts the fan-out unit design for each package on the panel to match actual die locations. Finally, the design files for each panel are imported to a lithography machine which uses the design data to dynamically apply a custom, Adaptive Pattern to each panel during the fan-out build-up process. Adaptive Patterning works by dynamically adjusting one or more build-up layers to accurately connect to the Cu studs protruding through the mold compound for each individual die in the molded panel.

After the Adaptive Patterning design files are created, fan-out processing can commence. The build-up proceeds through polymer 1, RDL, polymer 2 and UBM layers, with the lithography system implementing unique designs at the polymer 1 and RDL layers on a per panel basis. Finally, ball attach and package finishing are performed to produce singulated fan-out packages.

deca 1

The board level reliability was examined for a 8mm X 8mm package with 324 IOs on a 0.4mm pitch. The packages were mounted to 1mm thick printed circuit boards (PCBs) with non-solder-mask defined PCB pads. Standard JEDEC conditions were used for temperature cycling and drop testing. First cycling failure occurred at 665 cycles and with no failures observed up to 250 drops.

SPTS – Plasma Dicing

Plasma dicing is attracting significant interest within the semiconductor industry as a viable alternative to conventional singulation methods using saw blades or lasers. Plasma dicing promises benefits such as increasing wafer throughput, die per wafer and die yields (due to low damage processing). For small die, in particular, where the time required for a high number of mechanical slices in “series” can be substantial, a “parallel” process such as plasma dicing which etches all dicing lanes simultaneously, can significantly increase wafer throughput.

Maximum benefits are gained when plasma dicing is “designed in” from the beginning. With dicing lanes defined by photolithography, these lanes can be narrower than the width of a dicing blade, saving valuable silicon real-estate which can be used to increase the number of die per wafer. Also, the designer can make sure that dicing lanes are free from metals and other layers which can hinder plasma etching. This is often quoted as the prime challenge which prevents implementing plasma dicing in an existing production scheme.

IMEC / KLA Tencor

IMEC / KLA Tencor shared their results on investigations to determine the best way to insure µbump presence and co-planarity. µbump dimensions are being scaled down to 20 um pitch (10 µm in width and 8 µm high). For die-to-die and die-to-wafer stacking, the need for highly accurate and repeatable measurement of µbumps at both die-level and wafer-level is a must for this technology to become a viable industrial option.

Bump co-planarity is defined as the difference between the heights of the tallest and the shortest µbump within a die as shown below.

IMEC 1

A failure to properly characterize the co-planarity of each die and detect defects of interest such as damaged, missing or mislocated bumps can lead to the wrongful classification of the die as suitable for asembly. This may have a number of yield-affecting consequences during stacking, such as open and short circuits, die cracking and thermal sinks. As the number of die in a typical die stack increases, a single falsely classified die will affect the entire product.

One of the challenges in constituting a meaningful subset for measurement is to define a population of µbumps which is large enough to be statistically significant and to select µbumps from areas in the die which will represent height range and coplanarity of the full die.

Nanium / EVG

Nanium and EVG shared some information on Temporary Wafer Carrier Solutions for Thin FOWLP and eWLB-based PoP.

In order to achieve a cost competitive position related with other packaging technologies, FOWLP has been using 300mm diameter reconstituted wafers, which brings challenges related with its mechanical and thermomechanical properties like wafer bow, wafer warpage and wafer expansion. Nowadays, more FOWLP designs require reconstituted wafers with thickness below 400um. When wafer thickness drops below 400~450um, the reconstituted wafers acquires a flexible behavior that does not allow self-supporting handling anymore.

Adding to this challenge, the need for RDL processing on both sides of the eWLB wafer, for 3D and PoP constructions, requires the temporary protection of one RDL side while the other is being built. Solutions such as temporary wafer bonding for 2.5/3DIC technology , cannot be copied-exact for eWLB wafers because of the very high and non-linear thermomechanical behavior of such wafers and to the temperature limitations the molded material imposes. For example, Si wafers failed as carriers due to the mechanical mismatch to eWLB wafers and with adhesives with bonding process temperature above 200ºC . The selection of carrier wafer and adhesive material are key elements to the success of any temporary bonding and debonding technique for eWLB or fan out in general.

Based on their studies we are not told what the preferred carrier or temp adhesive are, but we are led through several solutions and told what properties lead to the best results.

For all the latest on 3DIC and other advanced packaging options, stay linked to IFTLE…

IFTLE 266 IMAPS Goes Searchable; GaTech Interposer Conf Part 3

Monday, December 14th, 2015

By Dr. Phil Garrou, Contributing Editor

IMAPS now “Googleable”

Of upmost importance to researchers at Universities, Research Institutes and even Commercial Companies is the ability of others to find their publications.

For years, a pet peeve of mine with IMAPS (the International Microelectronics and Packaging Society) is that once your work was published it was …well…lost. Mind you I was Technical VP and then President of the Society in 1997 so I’m not some complaining outsider. I have been saying this for more than 20 years. Certainly their journal and proceedings are “archival” in the technical sense of the word. Both are bound and printed and available to individuals and libraries for posterity, but many of their conferences containing key publications are only available if you know they exist and go to the IMAPS web page to download them.

In the 1990s most of the key papers on multichip modules (MCMs) were put into the conference of the same name that many of us sponsored through IMAPS. It was a great Conference, but try finding those papers now unless you have copies of all those proceedings.

Nothing has changed more in my lifetime then how we write reports and share data. In 1975, my first year in industry, we wrote report drafts on yellow legal paper and gave them to the office secretarial pool to type for us. They went back and forth a couple of times (since they couldn’t read my handwriting) and figures were added after they were drawn on a draft board.

Literature searching was done in the library where you combed through books and journals till you found what you were looking for. Once you found a key paper you went through all the references in that paper and went backwards like that till you were pretty sure you had found everything that was worthwhile.

All that changed with the computer and the internet. The computer which we got individually in our offices ~ 1985 (best I can recall) caused the unemployment of a lot of young women in the secretarial pool, but it sure increased my productivity in terms of putting a report together. Internet searching of the scientific literature came a bit slower, but by the late 1990s, or certainly by the time Google Scholar came into being in 2004, most researchers simply put their queries into the Google and up popped more references than you could read.  Everything was now available, well everything that Google searched. You can also easily see where this leads. If everyone only references things that are searchable in Google, then after a few years the only references you can find are those that are searchable by Google. Not so great for scientists publishing in non searchable sources.

The Europeans caught on to this problem first and we saw IMAPS conferences in Europe requesting co-sponsorship of IEEE so that their work would be put into IEEE Explore (yes its Google searchable).

It has taken awhile, but after a lot of bitching by myself and others and a lot of hard work by IMAPS staff everything is now searchable back to 2010. Not only the journal and the annual fall meeting but also key conferences like the Device Packaging Conference (DPC). YES – all the slides presented at the DPCs (since 2010) are now searchable and downloadable. I have tested this out myself and sure enough Google now finds them. For more details try www.imapsource.org/

Georgia Tech Interposer Conference (GIT 2015)

Finishing up our look at the GIT, lets look at Intels EMIB and the SPIL / Xilinx SLIT

EMIB

Intel is still keeping design flow and ground rules for EMIB (embedded multi die interconnect bridge) close to the vest and I did not see much new from Bob Sankman.

emib 1

Certainly the EMIB eliminates a chip attach operation since there is no Si interposer, but the BGA substrate sure looks a whole lot more complex to me. It certainly is an elegant solution, but I’m not convinced it is the low cost solution till I hear from customers what these modules will really cost. It certainly is of interest that Altera has announced a Stratix 10 to be done with EMIB.

emib 2

SLIT

Xilinx and SPIL were he first to announce TSV free high density interconnect more than a year ago. See IFTLE 215, “STATS Acquisition; Will SLIT replace TSV?”]

Xilinx indicates that the UMC/SPIL version of CoWoS, SSIT is ready for production.

SLIT 1

SLIT offers

- 65nm BEOL design rules                                                                                                                                             – non TSV interconnection                                                                                                                                                    - reduced CAPEX                                                                                                                                                                              - less inspection metrology steps                                                                                                                                             – SLIT patent issued to Xilinx

Xilinx compares SLIT to other solutions below:

slit 2

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

 

IFTLE 264 2015 GaTech Interposer Conf Part 2: The Status of Glass

Tuesday, December 8th, 2015

By Dr. Phil Garrou, Contributing Editor

The GaTech group ad many of their members have been studying the applicability of glass as 2.5D interposers for several years now. Some of the papers presented at this year’s meeting updated the industries status in this area.

LPKF Vitrion

LPKF Vitrion updated the attendees with their latest Through Glass Vias (TGV) technology status which is shown below.

LPKF 1

Shinko

Shinko updated their 2014 presentation on the status of Glass interposer R&D and manufacturing. Shinko is looking at glass as an alternative to silicon interposers. Their proposed process flow is shown below.

shinko 1

An example of a fully assembled glass interposer is shown below.

shinko 2

Shinko points out that there are voids inside the TGVs and they are very difficult to avoid. These voids increase the via resistance ~ 8.5%. They are in the process of determining what the acceptable void content is.

shinko 3

They are capable of 2um L/S RDL on the glass. They are in the process of reliability studies and failure analyses.

They are currently examining 250mm sq panels which increase unit production 2.7X vs 200mm wafers.

Unimicron

DC Hu from Unimicron shared their perspective on glass technology readiness. Hu lists the following requirements for glass mass production readiness:

Based on 510 x 510mm panels and 2/2 L/S fine line capability

- glass process readiness

  • Thin glass handling
  • Via forming technology
  • Via filling technology

- production equipment readiness

- reliability

He compared TGV formation from Via Mechanics, LPKF, Corning, Schott and Asahi Glass and via filling by seed and plate vs screen printed paste technologies. The paste technologies appear capable of 20um vis on 50um pitch.

While plating can be done on a 500mm sq panel, fine line patterning (2um L/S) requires a large panel stepper.

unimicron 2

Technology status vs silicon is shown below.

unimicron 3

TDK

TDK discussed what they claim is the first glass based Rf modules. Rf integration is clearly the key enabler for next gen smartphones. Key technologies for Rf modules are shown below.

TDK 1

The glass Rf module concept, which is being developed with GaTech, is shown below.

tdk 2

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…