Part of the  

Solid State Technology

  Network

About  |  Contact

IFTLE 261 Consolidation Continues; the Info on InFO?; RTI 3D ASIP

By Dr. Phil Garrou, Contributing Editor

Consolidation in our maturing industry is the ONE most important this that is happening to microelectronics in the 21st century because this is/will set the playing field for everything that follows. Many of you will be working for massive new companies soon whether you know it or not. This is something you really should be paying close attention to.

LAM Acquires KLA_Tencor

Consolidation continues with the recent announcement that Lam will acquire KLA-Tencor in a cash and stock transaction. The combined company will combine Lam’s capabilities in deposition, etch, and clean with KLA-Tencor’s capabilities in inspection and metrology. The combined company will have ~ $8.7B annual revenue making it roughly the same size as AMAT.

There will likely be opposition from some in the semi industry but probably less so than for the AMAT/TEL proposed merger since there is really little overlap in their focus markets.

Western Digital (WD) to Acquire SanDisk

The hard disk drive segment of our industry reached maturity ~ 2011. The hard disk drive business started in the 1960’s. Since then the > 200 companies who have been in the business competed on data density and latency and smaller form factors. Most of that industry has long since vanished through bankruptcy, mergers and acquisitions. As expected for a mature industry segment there are now 3 surviving manufacturers – Seagate, Toshiba and WD. Seagate acquired Samsung’s HDD business in 2011; Western Digital (WD) merged with Hitachi’s HDD business in 2011 and Toshiba acquired Fujitsu’s HDD business in 2009. This divided up the HDD market into WD 48%, Seagate 40% and Toshiba 12%.

Growth in mature industry segments requires acquisitions in aligned fields. Thus it could have been expected that WD would make a move into other types of data storage. WD’s acquisition of SanDisk gives the company an instant foothold in the global, non-volatile NAND flash memory market.

With the PC HDD business in decline due to both a weakening PC market and solid state drives (SSDs) making major inroads into that market, WD needed access to NAND storage technology both for laptops/desktops and to maintain competitiveness with NAND players in the enterprise space. This acquisition will allow WD to expand its participation in higher-growth memory storage segments.

It is reported that WD will have to raise $18.4 billion to finance the $19B SanDisk acquisition. In September WD announced that Chinese state-backed Unisplendour Corporation ( a subsidiary of Tsinghua Holdings ) would be investing $3.8B for 15% of WD “to help facilitate growth and future strategic initiatives.”

Sony Acquires Toshiba’s CMOS Image Sensor Business

Toshiba has announced that it will sell its image sensor business to Sony for ~ $166MM and pull out of the sensor business. For Sony, the acquisition of Toshiba’s image sensor business would further solidify its already dominant position in the industry where it already controls 40% of the market.

For those of us that have been following 3D with TSV since its inception, we recall that Toshiba was responsible for one of the early milestones, namely it was Oct 2007 that Toshiba announced the commercialization of their “chip scale camera module” which used “through chip vias.” Although it was only a one layer device, it marked the first mainstream commercial use of TSV in the silicon chip industry. By the way that was reported in one of my very first blogs in PFTLE, the predecessor to IFTLE which ran for several years in the now defunct Semiconductor International magazine. At that time PFTLE predicted that the CMOS imaging chips would eventually be broken up into functions and stacked. Sony brought that concept to commercialization a few years ago. [ see IFTLE 172, “IFTLE 172 Sony TSV Stacked CMOS Image Sensors Finally Arrive in 2013” ]

TSMC InFO

What’s the inside info on InFO. Try as you might, despite the significant press it has received, you cannot point to a publication that clearly outlines the process flow for TSMC’s InFO package. I have been asked whether it is chips first or chips last and all I could answer was: “Good question.”

Well, sources in Asia have leaked the following process flow to me. Although I cannot guarantee this is the actual TSMC InFO process flow (until Doug Yu confirms it) I’ll none the less show it to you since it is a quite interesting flow. The answer to the question for this process flow is chips first or interconnect last. Die are placed face up, pillars are plated on die and then molded. Routng to the package BGA balls is through mold vias (TMV). The wafer is then polished down to reveal tops of Cu pillars and standard” RDL is processed up from there. Ability for finer features appears to come from more planar starting surfaces and better controls of photo processes. IFTLE would guess that warpage is the major problem for this process flow.

InFO

3D ASIP Conference 12 Years and Going Strong

As it has for the last decade, 3D ASIP will once again close out the packaging conference season with its mid December 3DIC focused meeting outside of SF.

The 12th annual 3D Architectures for Semiconductor Integration and Packaging, or 3D ASIP as it has become known, will be held December 15-17, 2015, at the Sofitel San Francisco Bay Hotel in Redwood City, Ca. It is the longest running conference on 3DIC focused on commercialization and infrastructure.

The conference general chair and program coordinator is Dr. Philip Garrou, Microelectronics Consultants of NC. The technical co-chairs this year will be Professor Mitsumasa Koyanagi, Tohoku University, and Dr. Rama Alapati, director of packaging product management, GLOBALFOUNDRIES.

Matt Lueck of RTI International and Herb Reiter of EDA2ASIC Consultants have developed two half-day tutorials focused on temporary bonding/debonding and interposer design respectively. Presenters from CEA-Leti, HD Micro, Dow, TOK, Brewer Science, SUSS MicroTec and TOK will discuss the current state of the art in bonding and debonding technologies. The interposer design program includes presentations from Mentor Graphics, Cadence Design Systems, Ansys, E-System Design, Zuke, and eSilicon.

“This year, 3D ASIP will honor two trailblazers in 3DIC, Peter Ramm, Fraunhofer EMFT and Professor Mitsumasa Koyanagi, Tohoku University. They will be honored for their early pioneering work in the 1990s that set the stage for what we today know as 3DIC. Following the award ceremony, each recipient will deliver a short presentation on his group’s early work in 3DIC.

Screen Shot 2015-11-16 at 6.02.36 AM

 

Plenary presentations will be delivered by Brandon Prior, Prismark, discussing the status of 2.5/3D and other high density technologies; Rozalia Beica, Yole Développement, comparing and contrasting the new 3D memory architectures; and DC Hu, Unimicron, reviewing the transformation of substrate technology.

Screen Shot 2015-11-16 at 6.02.45 AM

 

The nine invited sessions cover topics including: Memory Stacks become Reality, Products and Production in the 2.5/3D Infrastructure, Equipment and Metrology, High Density Packaging without TSV, and Heterogeneous Integration.

Key presentations will include Hynix, Micron, Tezzaron and Toshiba discussing their new 3D stacked memory products; Xilinx/SPIL, Amkor and TSMC discussing their non TSV high density solutions; AMD discussing the commercialization of Fiji graphics modules with HBM memory stacks. Dan Green of DARPA discussing their DAHI heterogeneous integration 3D platform and Sony discussing their new stacked image sensor technology.

For more information on the conference agenda, visit the conference website at www.3dasip.org.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

 

Leave a Reply