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IFTLE 258: IEEE 3DIC Sendai Japan; GINTI

By Dr. Phil Garrou, Contributing Editor

The official IEEE 3DIC meeting started in 2009. It rotates from the USA to Europe to Asia on an annual basis. I say official because we all know that “3DIC” has been a buzzword, so every electronics conference in the world has sought 3DIC content, including competing IEEE conferences.

This year’s conference was in Sendai Japan and headed up by Mitsu Koyanagi from Tohoku University. Many of you may not know that Koyanagi-san is viewed as one of the fathers of 3DIC based on his early work in the late 1980s, such as his famous paper “Roadblocks to Achieving Three Dimensional LSI”. He has been working on the three key technologies for 3DIC (thinning, TSV, and bonding) since that time. He will be receiving a “Pioneering Award” for his 3DIC activities this fall at the 3D ASIP Conference which I will be chairing. [Link]


IFTLE has discussed GINTI previously (see IFTLE 166, “IEEE 3DIC Conf part 1; 3DIC panel discussion; Ginti; Novati”).

One of the plenary presentations at this year’s IEEE 3DIC conference was “Advanced 2.5D/3D Hetero-Integration Technologies at GINTI, Tohoku University” by KW Lee, Koyanagi-san, and co-workers, detailing the activities at the University and the prototyping spin-out.

The Global Integration Initiative (GINTI) is 8/12-inch R&D foundry fab for the R&D of 2.5D/3D integration technologies and applications. GINTI provides a process development infrastructure in a manufacturing-like fab environment and “low cost”, prototyping of proof of concepts using commercial/customized 2D chip/wafer, and a base-line process. The figure below shows their 8/12-inch 2.5D/3D integration process equipment

State-of-the technologies include design, layout and mask making to wafer thinning, forming of TSV on chip/wafer (front side/backside TSV), redistribution routing, both side micro-bump formation, chip/wafer stacking, failure analysis, and reliability testing.

GINTI can provide 3D prototype LSI stacking using commercial 2D chips by die-level 3D hetero-integration, backside TSV formation and various stacking (C2C C2W, W2W, and self-assembly) technologies.

IFTLE258_Fig1GINTI mainly focuses on via-last backside TSV approach, because they feel it is a better solution for heterogeneously integrating different function, size, and material devices, with better flexibility for commercial chip/wafers.

Their process flow for via-last backside TSV fabrication is shown below. The incoming LSI device wafer with metal bumps is temporarily bonded onto a support wafer. Then the Si substrate is thinned to target thickness from the backside by grinding and CMP. After via patterning on the ground surface, the deep Si trench is formed from the backside by RIE processing until the first level metallization layer (M1) is exposed. Oxide liner is deposited via holes and the bottom oxide liner in via hole is selectively etched by dry etching to re-expose the M1 layer. Next, the deep trench is filled with Cu by electroplating after dep of barrier and seed metal layers. Re-distribution layer (RDL) is then formed on the backside and metal bumps are formed on the RDL by electroplating. Finally, the support wafer is de-bonded from the thinned LSI wafer.

IFTLE258_Fig2To create new 3D hetero-integrated systems, they have developed die-level 3D integration technology as shown below. Commercially available 2D chips with different functions and sizes, such as those of sensor, logic, and memories which were fabricated by different technologies, are processed to form TSVs and metal micro-bumps and integrated to form a 3D stacked chip in die level.

IFTLE258_Fig3The image below shows a 3D stacked image sensor chip comprising three layers of CIS, CDS, and ADC chips for high-speed image sensor systems.

IFTLE258_Fig4For all he latest on 3DIC and other advanced IC packaging solutions stay linked to IFTLE…

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