Part of the  

Solid State Technology

  Network

About  |  Contact

IFTLE 251 3DIC NAND vs 3D V-NAND

By Dr. Phil Garrou, Contributing Editor

A few years ago in IFTLE 62, we laughed when EE Times reporters got confused and unknowingly compared 3DIC to 3D finfets thinking they were the same thing. Well, things have now gotten even more confusing as the key NAND memory manufacturers have announced commercialization of vertical – NAND memory products which some are calling 3D NAND.

3D technologies

We have noted before that 3D ICs can be categorized as either (A) 3D Stacked ICs (3DIC), which refers to stacking and bonding thinned IC chips using TSV interconnects, or (2) monolithic 3D ICs [see IFTLE 177, Monolithic 3DIC….] which use sequential fab processes to realize 3D interconnects at the local levels of the on-chip wiring hierarchy which result in direct vertical interconnects between device layers. V-NAND is an example of the monolithic approach.

Toshiba TSV stacked NAND

Last week, in IFTLE 250, we noted that Toshiba had just announced the world’s first NAND flash memory packages, which stack eight or 16 dies of NAND flash memory devices and feature 128GB or 256GB capacities. Toshiba’s new stacked NAND flash packages integrate (16) 128Gb NAND memory devices connected together using through silicon vias. The multi-layer chips by Toshiba feature 1Gb/s data rate, 1.8V core voltage and 1.2V I/O voltage. The new packages use 50 percent less energy on write operations, read operations, and I/O data transfers than Toshiba’s current products.

The NAND flash memory chips are designed for low latency, high bandwidth and high IOPS/watt flash storage applications, including high-end enterprise SSD. For example, (64) 256GB multi-layer chips would provide 16TB of NAND flash storage, but in order to build such a drive a special controller and other peripherals would be needed.

Toshiba did not say if or when it plans to release its new TSV-based NAND flash memory devices commercially.

PMC Sierra had a working SSD demo at the 2015 Flash Memory Summitt which used the new Toshiba TSV stacked memory (see below). [link] They report that the upfront costs are minimal ( prices for these TSV stacked NAND chips have not been released publically) compared to the long term costs due to power consumption differences. PMC Sierra demonstrated a significantly higher power efficiency for the TSV flash vs standard non-TSV flash for high end enterprise storage. Such power efficiency would also positively impact consumer notebook battery life.

PMC Sierra SSD PMC Sierra SSD

V- NAND

Vertical NAND memory devices, V-NAND, which some like Intel are calling 3D NAND, are fabricated sequentially and are connected on the cellular level as they layers are built.

Samsung has been working on V-NAND the longest (over a decade) announcing V-NAND based SSD, for use in enterprise servers and data centers, in 2013 and commercializing a 1 TB SSD last summer. Soon after Toshiba, SK Hynix and the Micron / Intel JV IMFT also announced V-NAND roadmaps.

From what has been publically reported, IMFT and Hynix have chosen to stack the current floating gate cell architecture ( the architecture for the vast majority of current 2D NAND) while Samsung and Toshiba have each chosen completely new vertical architectures for their V-NAND technologies. For those with interest, a comparison of these architectures has been published by NCTU Taiwan [link]

So, it looks like NAND can be manufactured both by TSV based 3DIC stacking and by 3D monolithic fabrication.

Are the advantages of TSV based NAND significant enough to compete with monolithic V-NAND which is being commercialized by all the key NAND suppliers ?

What applications would TSV stacked NAND be superior in?

Will Toshiba really commercialize two competing memory stack technologies at the same time?

As these answers become apparent, we will let you know.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE…

One Response to “IFTLE 251 3DIC NAND vs 3D V-NAND”

  1. Bill Says:

    Phil,

    I think we will need to wear 3D glasses to fully understand what 3D options were used to implement a product.
    :)

    See you mid December at 3D ASIP.
    Bill

Leave a Reply