Part of the  

Solid State Technology

  Network

About  |  Contact

IFTLE 248 ECTC 4 Oxidation of EMC in Thin Packages; Compression Molding Large Panels; TSV Noise Coupling in 3DIC

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 ECTC.

Freescale – High Temperature Storage of Ultra-Thin Molded Array Packages

Ultra-thin molded array packages (TMAP) with package thickness ≤ 500 μm are desirable for applications where system integration space is limited. Such ultra-thin packages require careful selection of the epoxy molding compound (EMC) to control package level warpage.

In this presentation, the ultra-thin package (8 mm x 8mm) had an EMC thickness of 0.250mm, substrate thickness of 0.1mm. This package was found to exhibit tensile warpage of 160μm after 175°C, 500 hrs of high temp storage (HTS).

The primary mechanism for this warpage behavior was found to be thermal oxidation of the EMC in HTS. These conditions caused thermo-oxidative crosslinking leading to densification and shrinkage of the EMC inducing stresses leading to package warpage. Oxidation also changed the CTE and elastic modulus of the EMC making it more brittle and stiffer.

Cross-sectioned samples showed that the packages subjected to 175 °C, 500 hrs had a “dark brown” appearance closer to the package edges and progressing towards the die region (see below). This was not seen for the T0 samples. This dark brown area is due to EMC that has been oxidized under the high temperature exposure. Oxidation is proportional to time, temp and exposed surface area. Thus thinner packages show more of an impact of the same time/temp oxidation conditions than thicker packages since a higher % of the overall material present would be oxidized.

This shrinkage of the outer layer of EMC causes stress on the package which generates increased warpage of the package.

oxidized EMC

Fraunhoffer IZM & TU Berin – Compression molding for Large Area Panel Processing

The group at Fraunhoffer IZM and Tech Univ Berlin have studied large area (18 x 24”) compression molding of panalized packages. The large panel size was selected to achieve process compatibility with cost efficient PCB processes. They examined the so-called “mold first” process which starts with die assembly on an intermediate carrier followed by overmolding and debonding of the molded wafer/panel from the carrier. The redistribution layer based on e.g. thin film or PCB technology is finally applied on the reconfigured molded wafer/panel.

Using an ASM Siplace CA3 5680 chips were placed on the panel with an assembly speed of around 6500 chips/hr. An 8×8 mm, 2-chip package consisting of two 2×3 mm chips the test vehicle.

They used a APIC Yamada molding tool with a cavity size 24”x18” and thickness range from 100 – 5000μm. The fig below shows the principle of compression molding with mold cavity in the upper tooling and the reconfigured wafer in the lower tooling with liquid encapsulant.

comp mold

EMC Materials can be can be either liquid, granular or sheet compounds. Mold embedding materials should have low chemical shrinkage, low cure temperature and match thermo-mechanical properties for low warpage of the molded panel and low die shift after molding.

Both the liquid and granular material underwent a significant change in mechanical properties after post mold curing (PMC) since the curing reaction is NOT complete after leaving the molding machine. Their data indicates that heating and cooling the molded panel before PMC and carrier release should be avoided due to CTE mismatch and the related length changes between silicon dies, carrier material and moldings compounds. Such induced stresses causes a high risk for cracks in the molded panel especially when it is not fully cured.

They report that the most important requirement on the mold embedding process on large panels is the positional accuracy of the embedded dies after mold and cure.

IMEC – Noise Coupling between TSV and Active Devices

IMEC notes that TSVs can introduce noise coupling arising from electrical coupling between TSVs and the active devices. They investigated the TSV noise coupling to FinFETs and planar transistors up to 40 GHz.

By analyzing and comparing the impact of TSV noise on FinFET and planar device performance, the dominant coupling mechanisms were identified. For planar nMOSFETs, noise amplification through the bulk transconductance dominates for the ON state, leading to large noise coupling. For FinFETs the main coupling mechanism was capacitive even in the ON state. They conclude that nFinFETs have better noise coupling immunity than planar nNMOSFETs, i.e. TSV noise coupling to FinFET device is 20dB smaller than planar device at 1GHz and 4-8dB smaller at 40 GHz. They explain that the main reason for improved FinFET noise immunity is that the FinFETs are less sensitive to substrate bias due to the stronger gate control w.r.t. planar MOSFETs.

They have also investigated four different TSV architectures to predict their impacts on the noise coupling: 5um/50um via-middle TSVs with 200nm oxide liner; scaled 3um/50um via-middle TSVs with 200nm oxide liner; 5um/50um via-middle TSVs with 400nm oxide liner; and via-last TSV architecture with thick (3um) polymer liner (“Donut” TSV).

They conclude that scaling the TSV diameter, using thicker liner materials, and polymer based liner materials with smaller dielectric constant all reduce the coupling level mainly at low frequencies where TSV liner capacitance is the dominant factor on noise coupling. At 100 MHz, for the 3/50 um and “Donut” TSVs, the noise coupling reduces by about 4dB and 20dB respectively.

They conclude that In order to extract the KOZ accurately, coupling induced current variations must be considered together with the stress induced current change. Stress induced current change decreases rapidly with increasing distance; i.e. when the active device is 20 um away from TSV, the stress induced current change is close to zero for both planar and FinFET devices.

However the coupling induced current change decreases with distance much slower, which means the noise coupling can have significant influence on the KOZ. When an active device is located at 10um away from TSV, the current change induced by TSV stress is only 0.2% for FinFET device and 0.6% for a planar device, but these values increase to 2.23% and 3.55% when the impact from TSV noise coupling is added up at 10 GHz (2.03% for FinFET device and 2.95% for planar device). They conclude that it is important to use noise mitigation techniques such as “substrate contact and guarding” to reduce the electromagnetic coupling effects in order to minimize the KOZ.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

Leave a Reply