IFTLE 236 IMAPS DPC Part 3: Yole Update on FOWLP and Embedded Packaging
By Dr. Phil Garrou, Contributing Editor
Continuing our look at the IMAPS Device Packaging Conference:
Based on his new Yole report “Fan out and Embedded Die: Technology and Market Trends,” Jerome Alzemer updated the IMAPS audience on the Fan Out and Embedded die marketplace.
Embedded Packaging refers to many different concepts, IP, manufacturing infrastructures and related technologies. The two main categories of embedded packages are (1) those based on a molded wafer infrastructure such as FOWLP and (2) those based on a PWB/PCB laminate panel infrastructure.
Fan-out WLP are “re-configured” by placing known good ICs active face down on a foil and by over-molding them. These wafers are then flipped and processed in the wafer fab with RDL / ball placing and diced.
For chip embedding in laminate, known good ICs are picked and placed on top of an organic layer of Printed circuit board and subsequent layers are laminated on top. Regular PCB manufacturing operations then take place on the panel containing the embedded ICs. These generic process flows are contrasted in the figure below.
Fan Out WLP (FOWLP)
Unlike Fan In WLP which has been commercial since the late 1990’s, FOWLP is not constrained by die size, and thus can offer an unlimited number of interconnects for maximum connection density. One can also achieve finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market.
Commercialization of the Infineon e-WLB (embedded wafer level BGA) technology started in 2009 with single die packages for cell phone baseband chips. The Infineon technology was later licensed to OSATS Nanium, STATSChipPAC and ASE thus creating a multi sourced infrastructure.
A similar process called Redistributed Chip Packaging (RCP) was developed by Freescale during the same time period. It was subsequently licensed to NEPES but has not yet reached HVM. Other developing FOWLP technologies including those of TSMC (called InFO), SPIL and J- Devices are approaching commercialization but will initially lack the multi-sourcing available with eWLB.
The second generation of FOWLP are multichip packages including PoP and SiP configurations. These are generating increased interest in this packaging approach.
Technical Challenges, such as warpage, die shift, chip-to-mold non planarity and topography, remain significant limitations. FOWLP requires specific re-design vs FC-CSP solutions which are more flexible and mature.
The sweet spot for FOWLP application is restricted to die that need more I/O at a given pitch than can be accommodated by the the chip dimensions otherwise fan-in will meet the requirements.
Laminate Embedded Die
Laminate Embedded die packages are not widespread yet. They are currently limited to low I/O count die. AT&S and TDK/Epcos have a DC-DC converter in production for TI since 2010 but no other HVM products have appeared since then. Such laminate embedded die packages are currently a niche technology in the wireless and mobile markets.
AT&S and TDK-EPCOS are collaborating on standardization of products, which they see as necessary to obtain better acceptance of this packaging format.
Other players such as Taiyo-Yuden, Unimicron and DNP have proposed products such as camera modules, MEMS, DC-DC convertors, RF modules, etc. Few production products have appeared reportedly due to the absence of standards, lack of multiple sources, and high prices due to low yield.
As of 2014, Yole estimates a market of around $14MM driven by AT&S with TDK having a minor market share.
Initial commercialization of Embedded Die Package technology has started but is currently limited to low pin-counts, small die-size, low-cost, power, RF and mixed signal chip applications.
Potential exists for entering the power, RF and mixed signal chip applications but standardization and multiple sources are lacking. Yole does not expect the technology to near HVM before 2016 at the earliest and this will require the appearance of standardized, more complex integrated SiP modules from multiple sources.
Challenges for Laminate Embedded Die Packaging
Supply chain evolution and process standardization are the main challenges for Embedded Die package technologies.
- Total accessible market is currently limited by current poor pad pitch performance
- It is not yet clear whether improving resolution to produce better pad pitch will require moving to higher cost manufacturing tools which would negate the attempt to use laminates mature manufacturing flow to achieve low costs.
- Without a defined supply chain and an accepted process flow, multi-sourcing and cost reduction are not possible
- HVM is required to reduce costs to acceptable levels
FOWLP and Laminate Embedded Die are complementary technologies. That situation might change if Embedded Die achieve higher resolution, but that currently is not the case. They are compared in the figure below.
A complete outline of the Yole report can be found here [link]
For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…