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Archive for April, 2015

IFTLE 236 IMAPS DPC Part 3: Yole Update on FOWLP and Embedded Packaging

Thursday, April 23rd, 2015

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IMAPS Device Packaging Conference:

Yole Developpement

Based on his new Yole report “Fan out and Embedded Die: Technology and Market Trends,” Jerome Alzemer updated the IMAPS audience on the Fan Out and Embedded die marketplace.

Embedded Packaging refers to many different concepts, IP, manufacturing infrastructures and related technologies. The two main categories of embedded packages are (1) those based on a molded wafer infrastructure such as FOWLP and (2) those based on a PWB/PCB laminate panel infrastructure.

Fan-out WLP are “re-configured” by placing known good ICs active face down on a foil and by over-molding them. These wafers are then flipped and processed in the wafer fab with RDL / ball placing and diced.

For chip embedding in laminate, known good ICs are picked and placed on top of an organic layer of Printed circuit board and subsequent layers are laminated on top. Regular PCB manufacturing operations then take place on the panel containing the embedded ICs. These generic process flows are contrasted in the figure below.

FO & embbedded process flows

 

Fan Out WLP (FOWLP)

Unlike Fan In WLP which has been commercial since the late 1990’s, FOWLP is not constrained by die size, and thus can offer an unlimited number of interconnects for maximum connection density. One can also achieve  finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market.

Commercialization of the Infineon e-WLB (embedded wafer level BGA) technology started in 2009 with single die packages for cell phone baseband chips.   The Infineon technology was later licensed to OSATS Nanium, STATSChipPAC and ASE thus creating a multi sourced infrastructure.

A similar process called Redistributed Chip Packaging (RCP) was developed by Freescale during the same time period. It was subsequently licensed to NEPES but has not yet reached HVM. Other developing FOWLP  technologies including those of  TSMC (called InFO), SPIL and J- Devices are approaching commercialization but will initially lack the multi-sourcing available with eWLB.

The second generation of FOWLP are multichip packages including PoP and SiP configurations. These are generating increased interest in this packaging approach.

2nd gen FOWLP2014 FOWLP market share

Technical Challenges, such as warpage, die shift, chip-to-mold non planarity and topography, remain significant limitations. FOWLP requires specific re-design vs  FC-CSP solutions which are more flexible and mature.

The sweet spot for FOWLP application is restricted to die that need more  I/O at a given pitch than can be accommodated by the the chip dimensions otherwise fan-in will meet the requirements.

Laminate Embedded Die

Laminate Embedded die packages are not widespread yet. They are currently limited to low I/O count die. AT&S and TDK/Epcos have a DC-DC converter in production for TI since 2010 but no other HVM products have appeared since then. Such laminate embedded die packages are currently a niche technology in the wireless and mobile markets.

AT&S and TDK-EPCOS are collaborating on standardization of products, which they see as necessary to obtain better acceptance of this packaging format.

Other players such as Taiyo-Yuden, Unimicron and DNP have proposed products such as camera modules, MEMS, DC-DC convertors, RF modules, etc.  Few production products have appeared reportedly due to the absence of standards, lack of multiple sources, and high prices due to low yield.

As of 2014, Yole estimates a market of around $14MM driven by AT&S with TDK having a minor market share.

2014 embedded laminate mkt

Initial commercialization of Embedded Die Package technology has started but is currently limited to low pin-counts, small die-size, low-cost, power, RF and mixed signal chip applications.

Potential exists for entering the power, RF and mixed signal chip applications but standardization and multiple sources are lacking. Yole does not expect the technology to near HVM before 2016 at the earliest and this will require the appearance of standardized, more complex integrated SiP modules from multiple sources.

Challenges for Laminate Embedded Die Packaging

Supply chain evolution and process standardization are the main challenges for Embedded Die package technologies.

- Total accessible market is currently limited by current poor pad pitch performance

- It is not yet clear whether improving resolution to produce better pad pitch will require moving to higher cost manufacturing tools which would negate the attempt to use laminates  mature manufacturing flow to achieve low costs.

- Without a defined supply chain and an accepted process flow, multi-sourcing and cost reduction are not possible

- HVM is required to reduce costs to acceptable levels

FOWLP and Laminate Embedded Die are complementary technologies. That situation might change if Embedded Die achieve higher resolution, but that currently is not the case. They are compared in the figure below.

comparison

 

A complete outline of the Yole report can be found here [link]

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 235 KNS Update on Thermo compression Bonding and Dow Update on Mechanical & Laser Debondable Temp Adhesives

Thursday, April 9th, 2015

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 IMAPS Device Packaging Conference:

KNS – Thermocompression Bonding

Thermocompression bonding is required for the next generation fine pitch assembly technology. Applications for TCB are based on fine pitch Cu pillar technology with typical pitches of 40-60um and a pillar height of 30um. High accuracy placement is required to ensure high yield in these assemblies with placement accuracy of + 2um typical. Stacked memory products are driving the initial commercial volume in the technology, using TSV technology and thin die memory stacks 4+ layers in height. K&S projects that 75 to 80% of TCB bonders will be used for such memory stacks.

The key factors that have enabled TCB to move to HVM include:

- Equipment with higher UPH (units per hr) for lower cost per unit

- TCB equipment with excellent stability

- Advanced in-line process control

The TCB process is complex and can require 10 operations including temperature ramps, applied force, position control, and vacuum release. The process is being developed both for pre applied underfill and post assembly capillary underfill (CUF).

fig 1 process flow

 

The cost of TCB must be competitive with alternative assembly technologies which can only be achieved if the throughput and yield of the process is high. The critical requirement for adoption of TCB is cost reduction which requires high process UPH. Actual process time will vary based on the process selected but 1000 UPH is generally considered to be the threshold for cost effective production.

KNS concludes that:

-        The design of the bond head is critical to achieve fast temperature ramps and excellent uniformity

-        Planarity of the bond head to the target surface must be < 2um/10mm

-        Z-Position control during the bonding process must be +/- 1um

  • Heating bond head from 160C to 280C creates ~15 um Z movement which requires compensation to maintain accurate position

-        Accurate force applied before and during the bonding process is critical and the capability to switch between force and position mode during the process is key

-        Accurate high force is particularly critical for bonding with NCP or NCF. Depending on the die size and number of pillars, forces upwards of 300N may be required

-        Excellent Uniformity with rapid heating and cooling Rates is essential

-        Silicon die with TSV can be 50um or less, so TCB equipment must be designed to handle and bond thin silicon die without inducing mechanical damage.

fig 2

 

The KNS bonder and its specs is shown below.

fig 3 KNS bonder

 

Dow Chemical – Mechanical and Laser Debondable Temporary Adhesives

Temporary bonding is a major unit operation in the commercialization of 2.5 and 3DIC. The industry has been fine tuning this operation for nearly a decade and still have not come to consensus on what the appropriate low cost / high yield process should be. Temporary bonding can also be used in FOWLP  to maintain flatness during reconstituted wafer processing. Dow Chemical presented their take on mechanical vs laser debonding of temporary adhesives.

Working with Suss Microtec and Fraunhoffer IZM, Dow has studied mechanical vs laser ablation debonding as shown below.

fig 4

Mechanical debond has issues with:

  • Higher wafer stress due to higher required debond force
  • Potential wafer damage from debond process

Laser Debonding has issues with :

  • material modification to enable laser ablation
  • Potential wafer damage from unabsorbed laser energy

Laser debond reveals a considerable lower debond force than mechanical debond as shown below.

fig 5

Also of interest for laser debonding is the effect of wavelength on the debonding mode. A 248nm UV laser tend to cause delamination at the glass/adhesive interface whereas a 308nm UV laser tend to cause delamination at the substrate adhesive interface due to differences where the light is absorbed.

fig 6

 

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…