IFTLE 221 RTI 3D ASIP part 1: Global Foundries; Ga Tech
By Dr. Phil Garrou, Contributing Editor
It’s that time of year again when Hanna and Madeline wish a very Merry Christmas to all…
December is also the final 3D conference of the year, RTI Internationals 3D ASIP conference in Burlingame, CA. Over the next few weeks we will be looking at the remaining content from the GaTech Interposer Conference and the RTI 3D ASIP conference.
Zafer Kutlu of GlobalFoundries updated the audience on the “Status of Manufacturing and Design of 2.5D Packaging Technology” at his company. The GF open supply chain includes EDA and IP partners Cadence, Synopsys and Mentor Graphics and OSAT partners Amkor, ASE, STATSChipPAC and SPIL and memory stack supplier Hynix.
The ATACAMA test vehicle, was used for tool/line setup, base investigation on interposer design and processing, supply chain setup. The KALAHARI technology baseline qualification test vehicle, for CPI qualification and final inputs to DM and PDK.
Kutlu announced that they would be ready with PDK Rev 1.0 in 1Q 2015.
Muhannad Bakir of GaTech was invited to share his concepts on silicon bridge interconnects and 3D micro fluidic cooling solutions that he is working on for the DARPA ICECool program. Bakir was asked to “Bring the real Data” and that he did as you can see from the picture below.Bakir brought Data to 3D ASIP
Concept 1 is a linking interconnect technology that use self aligned silicon interposer tiles and bridges. The tiles are aligned using pyramidal pits etched in the silicon and mated with 300um solder balls (as shown below) The interposers can be linked and interconnected using the same ball and socket alignment concept. Connection between interposer and mother board or chip and interposer is made using the GaTech “spring” interconnects as shown. Although I am not yet sold on using the spring connection in HVM, we will keep an eye on this technology as it is developed.
The second concept pertains to microfluidic cooling for silicon interposer modules.
Silicon dice with electrical microbumps, fluidic microbumps and vias, and micropin-fin heat sinks were fabricated and flip-chip bonded on a silicon interposer. Micro pin fins are etched into the back side of the chip and TSV created in the pin fins to connect to the next level.
Compared to chips that are air cooled, the micro fluidic module shows significantly cooler operation (i.e. 98 C max vs 64 C max).
Stay tuned because working with Altera, they are creating such cooling channels in the backside of a live FPGA.
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