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Archive for December, 2014

IFTLE 221 RTI 3D ASIP part 1: Global Foundries; Ga Tech

Tuesday, December 23rd, 2014

By Dr. Phil Garrou, Contributing Editor

It’s that time of year again when Hanna and Madeline wish a very Merry Christmas to all…

H & M

 

December is also the final 3D conference of the year, RTI Internationals 3D ASIP conference in Burlingame, CA. Over the next few weeks we will be looking at the remaining content from the GaTech Interposer Conference and the RTI 3D ASIP conference.

Global Foundries

Zafer Kutlu of GlobalFoundries updated the audience on the “Status of Manufacturing and Design of 2.5D Packaging Technology” at his company. The GF open supply chain includes EDA and IP partners Cadence, Synopsys and Mentor Graphics and OSAT partners Amkor, ASE, STATSChipPAC and SPIL and memory stack supplier Hynix.

GF 1

 

The ATACAMA test vehicle, was used for tool/line setup, base investigation on interposer design and processing, supply chain setup. The KALAHARI technology baseline qualification test vehicle, for CPI qualification and final inputs to DM and PDK.

GF 2

 

Kutlu announced that they would be ready with PDK Rev 1.0 in 1Q 2015.

Ga Tech

Muhannad Bakir of GaTech was invited to share his concepts on silicon bridge interconnects and 3D micro fluidic cooling solutions that he is working on for the DARPA ICECool program. Bakir was asked to “Bring the real Data” and that he did as you can see from the picture below.

Bakir brought Data to 3D ASIP Bakir brought Data to 3D ASIP

Concept 1 is a linking interconnect technology that use self aligned silicon interposer tiles and bridges. The tiles are aligned using pyramidal pits etched in the silicon and mated with 300um solder balls (as shown below) The interposers can be linked and interconnected using the same ball and socket alignment concept. Connection between interposer and mother board or chip and interposer is made using the GaTech “spring”  interconnects as shown. Although I am not yet sold on using the spring connection in HVM, we will keep an eye on this technology as it is developed.

GT 1

 

The second concept pertains to microfluidic cooling for silicon interposer modules.

GT 3

 

Silicon dice with electrical microbumps, fluidic microbumps and vias, and micropin-fin heat sinks were fabricated and flip-chip bonded on a silicon interposer. Micro pin fins are etched into the back side of the chip and TSV created in the pin fins to connect to the next level.

GaTech 4

 

Compared to chips that are air cooled, the micro fluidic module shows significantly cooler operation (i.e. 98 C max vs 64 C max).

Stay tuned because working with Altera, they are creating such cooling channels in the backside of a live FPGA.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 220 GaTech Global Interposer Conference part 1 : Repeat After Me – “Panel Size, Equipment Set Cost and Yielded Throughput”

Monday, December 15th, 2014

By Dr. Phil Garrou, Contributing Editor

GaTech Global Interposer Conference

The 4th Annual Global Interposer Technology Workshop At GaTech gathered 200 attendees from 11 countries to discuss the status of interposer technology. It has become the one meeting where you can find all the key interposer layers including those representing glass, laminate and silicon. Some of the panel discussions I have seen discussing the pros and cons of various interposer alternatives have been at this meeting due to the broad technical scope of its attendees.

Joining Rao Tummala as co-chairs were Matt Nowak of Qualcomm and Subu Iyer of IBM.

Yole

Representing Yole Developpement I presented an update on 2.5/3D focusing on thee new 3D memory architectures which have been needed for silicon interposers to really take off.

Yole 1

 

The audience was also forced to endure my lecture on packaging nomenclature which is getting completely out of hand.

Leadframes, BGA substrates and pieces of silicon with high density wiring and TSV are all interposers. The term 2.5D was a joke and the term 2.1D or others such as 5.5D similarly are jokes with no technical meaning. What the laminate community is beginning to call 2.1D is simply a higher density BGA substrate.

yole 2

 

IBM

IyerIBM’s Subu Iyer, an IBM Fellow, IEEE Fellow and front end practitioner for many decades has been a long time supporter of this Global Interposer Conference.

Always one to speak his mind Subu was blunt and to the point on two key issues during the panel session at this conference; (a) interposer definitions and (b) the presumed interposer cost structure.

He agreed that 2.1, 2.5D etc. has no real meaning and is only confusing non packaging practitioners. Here is the now infamous exchange with Rao Tummala [link]

Subu: “I find the whole concept of 2.5D fairly atrocious. I have banned its use [in IBM].”
Rao: “what are you going to call it?”
Subu: “Interposers, like God intended it to be.”

While nomenclature is important to keep concepts straight, even more important was the discussion on the relative costs of silicon vs glass vs laminate interposers. Subu’s point was:

“…high density interposers will all cost the same whether glass or laminate or silicon…the cost is not materials dependent but rather density dependent”

This is a point  that I have been trying to make myself for a few years now on IFTLE since the concept of the glass interposer became all the rage. As Subu said, interposer costs will all be approximately the same if the densities are equal and the equipment sets are the same.  In the chemical industry, from whence I came, the rule of thumb was that raw materials were responsible for approx. 10% of the total cost.

The key is NOT that glass is a low cost material, but rather whether one can manufacture fine features on large glass panels . Panel size and equipment set cost and throughput (yielded) will determine the cost of glass interposers not (I repeat) not the fact that window pane is cheaper than a silicon wafer.

Low cost equipment to create high density features on  large panel substrates (which obviously won’t be silicon)  IS a worthy goal for both glass and laminate providers,  lets just not loose track of what the key factors are. PANEL SIZE…EQUIPMENT SET COST…THROUGHPUT

In fact, a t the 2011 GaTech Global Interposer Conference Yole Developpement predicted that panel lines would be required for 2.5D interposers to attain a low enough cost to be widely adopted in the chip packaging community [link]

GaTech Glass Panel Consortium

At the IEEE Global Interposer Technology workshop in Nov Rao Tummala announced the formation of a “Panel based Global Glass industry Consortium” for “low cost, ultra miniaturization, high performance and Si like ultra high IO interconnections to address both small and ultra small system needs such as smartphones, wearables, IoTs and medical systems.”

Tummala continued “ we started looking at glass in 2010….today we have 50 global companies involved…GaTech can now access the complete ecosystem to develop and apply this technology to single chips, with lower cost than todays packages, multi chip in 2.5D architecture, similar in IO pitch to todays Si interposers but at much lower cost and ultimately to 3D system architectures”

GaTech continued that they “are producing advanced 2D, 2.5D and 3D system packages in its 300mm panel facility and looks forward to transferring the technology to 510mm panel fabs.”

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 219 Amkor responds to Samsung Plated Mold Via; TSMC INFO factory, 3D Memory Stacks finally arrive

Tuesday, December 2nd, 2014

By Dr. Phil Garrou, Contributing Editor

TMV vs PMV

At the recent IMAPS conference, Samsung electro-mechanics compared their Plated Mold Via Technology (PMV) to the well known Amkor Through Mold Via  (TMV) technology. The two process flows are compared below.

samsung em 1

 

Samsung EM describes the driving force for this new technology as the added adhesion that they get by replacing the solder TMV fill with copper in the PMV.

Seeking input from Glenn Rinne of Amkor, IFTLE found out that Amkor has run both processes and seen that the laser formed vias have both cavities and protrusions in the via walls due to the filler in the mold compound. The cavities serve as a “roughness” which anchors the solder fill and the filler particles protruding into the vias actually shadow the deposition of seed layer when copper is plated into the holes so they concluded that the solder, which is “conductive enough” actually shows better adhesion and is a cheaper process.

TSMC Continues move into packaging

TSMC is purchasing a plant in Longtan, Taiwan from Qualcomm for $85MM and turning it into a facility devoted to the development of the advanced integrated fan-out wafer-level packaging (InFO-WLP) technology. TSMC could initiate manufacturing as early as 2016 on 16nm chips, but HVM date will depend on “customer demand” [link]

TSMC and Samsung battle for Apple and Qualcomm Orders

It is reported that both Apple and Qualcomm will likely buy a larger proportion of 14 nanometer smartphone chips from Samsung rather than TSMC beginning in the second half of 2015 [link].

Given that Samsung has more advanced manufacturing technology to produce fin field-effect transistor, the company is reportedly more likely to win Apple’s contract for A9 processor production, said research institute Bernstein Research.

The Commercial Times reports that Qualcomm has already started working with Samsung to develop the chips. The Economic Daily News adds that Qualcomm has already placed orders with Samsung.

3D Memory Stacks Finally Arrive

For those of you struggling with all the new memory architectures that have been announced, I recommend the recent article by Yole Developpement which details announcements by Hynix, Samsung, Micron and Tezzaron [link]. With the recent Samsung announcement of mass production of 64 GB DDR4 DIMMs that use TSV technology for enterprise servers and cloud-based applications, all three of the major DRAM memory manufactures, Samsung, Hynix and Micron, have now announced the commercialization of TSV based memory architectures.

yole

 

Different applications will have different requirements in terms of bandwidth, power consumption, and footprint. As we move into 2015 several industry segments have announced applications using the new memory stacks. Intel recently announced that their Xenon Phi processor “Knights Landing,” which will debut in 2015 will use 16GB of Micron HMC stacked DRAM on-package, providing up to 500GB/sec of memory bandwidth for high performance computing applications.  AMD and Nvidia have also announced the use of HBM in their next generation graphics modules like the Nvidia Pascal due out in 2016.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.