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IFTLE 216 3D ASIP Program; 2014 IMAPS part 2: MR for Amkor Copper Pillar Bumps

By Dr. Phil Garrou, Contributing Editor

3D ASIP

It’s that time of year again to be thinking about registering for the RTI sponsored 3D ASIP (Architectures for Semiconductor Integration & Pkging) which will be held at the Burlingame Hyatt on Dec 10-12 [link].

RTI ASIP has been focused on 3DIC and 2.5D for 11 years now. As we are now finally seeing  commercial commitment from the memory suppliers and the graphics module manufacturers hopefully we are observing 2.5/3DIC  finally taking off. Unlike other, more academic conferences, RTI ASIP has always been focused on the commercial and business aspects of bringing 3DIC to the market place.

This years program includes two special pre-conference symposia . A  ½ day symposia 2.5/3D IC design tools and flows led by Herb Reiter will include speakers from Cadence, Mentor, Apache design, GF, Rambus and Qualcomm. There will also be a half day tutorial on the current state of the art in 2.5/3D processing led by yours truly with “drill and fill” covered by Dean Malta of RTI; Temp bond and via reveal presented by Severine Cheramy of Leti and assembly presented by Laura Mirkarimi of Invensas.    As a special bonus, those attending the processing tutorial will receive a free copy of “The Handbook of 3D Integration Volume 3: 3D Process Technology” edited by Garrou, Koyanagi and Ramm.

The regular conference includes presentations by Micron, Xilinx, Nvidia, GF, Synopsys, Nanium, Unimicron ad many more . Of special interest should be the updates on their DARPA ICECool  3D cooling programs by Bakkir of GaTech and Gaynes of IBM Watson and the IoT (Internet of things) presentations by Beica of Yole and Schulz of the silicon integration initiative.

Hope to see you there.

Amkor – Extending Mass Reflow to Finer Pitch Copper Pillar Bumping

Another key paper from the recent 2014 IMAPS Conference in San Diego was by Fernando Roa of  Amkor concerned with extending the current processing envelope for Copper pillar bumping using mass reflow (MR).

Thermo compression (TC) is typically applied for copper pillar bumping. In general, it is a slower more expensive assembly process since each die has to be positioned and mated before moving on to the next die. A bonding head is typically used to hold the die flat and in alignment with the substrate while heat is applied to complete the connection. In general MR throughput is 2X that of MR.

In contrast, MR bonding places the die and then reflows them all at once.  Std FC attach and capillary underfill is shown below vs thermo-compression (TC) bonding.  TC typically underfills with non conductive paste (NCP) or film since capillary underfills are more difficult to use with copper pillar bumps because of their fine pitch.

amkor 1

 

Amkor typically uses the MR process flow for copper pillar bump (CPB) from 200 to 100um pitches with minimum changes to the standard process flow.

For fine bump pitch (b), since the bumps are much closer together there is less room to create solder mask defined pads as show below. Since the bump diameter is close to the typical width of the trace they are allowed to form connection directly on the trace.

amkor 2

 

While typical MR assembly relies on solder self alignment during reflow, MR of solder to trace is more difficult since self alignment to solder catch pads is not possible. In MR of fine pitch bumps the solder wraps around the trace in contrast to TC joints that typically show solder squeezing out of the joints because of the compression.

Very precise selection and control of die thickness, substrate construction and substrate finish is necessary to reduce or eliminate solder shorts and non wets. Roa indicates that Amkor efforts are underway to extend MR to finer pitch bumping activities.

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