Part of the  

Solid State Technology

  Network

About  |  Contact

Archive for October, 2014

IFTLE 214 Nanium’s Mamouth WLCSP, IBM Deal Done; Cu WB at TI

Wednesday, October 22nd, 2014

By Dr. Phil Garrou, Contributing Editor

Nanium

Most of us know of Nanium as a contract assembly house in Portugal who licensed the Infineon eWLB fan out technology and is supplying such packages on 300mm wafers.

NANIUM also has extensive volume manufacturing experience in WB  multi-chip memory packages, combining Wafer-level RDL techniques (redistribution) with multiple die stacking in a package.

nanium 2

In 2012 Nanium licensed the 300mm FC bumping and Spheron fan-in WLCSP technologies from Flip Chip International (FCI) [link]. After completing line setup and qualification for that technology, the company added the capability to manufacture fan-in WLP product.

Today, they call themselves a “Wafer Level Packaging solution provider” as more than 90% of their business is now WLP.

In May we discussed Nanium’s presentation “Wafer Level Fan-Out as Fine-Pitch Interposer” that proposed eWLB as an alternative to 2.5D silicon with sufficient capability for many applications in high volume at reasonable cost.  [ see IFTLE 194, “…… SEMI Singapore part 3: Nanium, Fujitsu, EVG”]

NANIUM has now announced commercialization of a 29nm, 25mm x 23mm (about the maximum reticle size allowed),  fan-in WLCSP  on 300mm wafers for customer  Custom Silicon Solutions (CSS).

CSS reports that such large dies are usually packaged in WB-BGA or FC-BGA with underfill material between bumped die and FC substrate for board-level reliability.

Naniums WLCSP has 1,188 solder balls on a  0.7mm BGA pitch. It has successfully passed more than 400 temperature cycles on board (-25 – +100 C). Die are 475um thick.

nanium

IFTLE Agrees that WLCSP technology has traditionally been limited to chips less than 7mm and the packaging community has been looking for technologies to allow the manufacture of greater than 10mm WLCSP.

ITLE has contacted Nanium for further “insight” and learned that they use 380um BGA solder balls that collapse to 300um stand off height after reflow. Reliability testing of the large WLCSP are done without underfill and do not have a polymer collar or similar technology improving their reliability. PBO based devices pass 400 cycles and PI based devices pass 600 cycles. Nanium does note that the customer is underfilling when assembling to the board “to be on the safe side.”

When asked directly what they key technology breakthrough was/is Naniums’s Steffen Kroehnert responded, “There really in not one big thing…there are a lot of small things…material dielectric choice makes a big difference…design features such as trace and pad design and size , copper area loading, Cu thickness, thick UBM and optimization of solder ball  alloy all contributed.”

IBM Deal Done

Every once in awhile I break with normal journalistic decorum and like a little boy in the school yard get pleasure from shouting “I told you so” (OK…maybe a little more than every once in awhile).  My little Italian grandmother (Nonna) told me not to gloat when you were right about something because no one likes such people… but it’s hard to resist. [For my non US readers, gloating is “…dwelling on one's correctness with smugness.”]

IFTLE came to the conclusion that IBM would sell off their semiconductor business several years ago when it became clear that future node fabs would cost far more to construct  ( $4-6B) than the IBM semi business was making on a yearly basis (~ $1B). These simple economics would eventually prevail. As they pulled so called “IBM friends and family” around them in NY a few years ago, it became clear that they were positioning to have one of these “friends” buy the business and become their supplier. It has been clear for more than a year that Global Foundries was the logical choice.

Some were shocked when rumors leaked that IBM was having to sweeten the pot with significant cash in order to get GF to take over their money loosing semiconductor operation. But, as I have explained previously, that’s what is required when  you take over a business that’s loosing ~ $2B / yr . What Global gets out of this deal is not the manufacturing capability or the customer list, but rather the people and the IP. Once they restructure I see this as a good deal for GF and for IBM employees who obviously were no longer required by their now ex employer.

IBM has now officially announced the deal with Globalfoundries [link].  IBM will pay GF $1.5B to take over their chip manufacturing operations, which will continue to produce processors used in IBM systems.

Recently reported revenues from IBM’s Systems and Technology segment, which includes the company’s computers, declined 14%. The company’s other hardware segment–the Power systems, based on IBM-designed computer chips, fell 12%.

Cu WB at TI

TI began shipping copper WB, which delivers a 40% increase in conductivity, in its products in 2008.  Today, all of TI’s assembly sites are running copper WB on all TI package types, including BGA, QFN, QFP, TSSOP, SOIC, PDIP and others.  Copper is currently 71 percent of TI’s total WB usage. Existing analog and CMOS silicon technology nodes have been qualified with copper WB, and all new TI technologies and packages are being developed with copper WB.

TI is currently shipping about two billion units of copper wire bond technology each quarter.  TI has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial.

TI 1

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 213 What’s New in Permanent Polymer Dielectrics: Dow, HD Micro, Zeon

Tuesday, October 14th, 2014

By Dr. Phil Garrou, Contributing Editor

It’s been awhile since we looked at what is new on the dielectric market so we checked with a number of dielectric suppliers and asked what was new in their product lines.

Dow Chemical

The old Rohm & Haas organization has been running the Dow Electronics Materials business for a while now, basically since they were acquired by Dow. I knew they would do well when I observed them make the ill advised low-K SILK product quietly go away.

They certainly have beefed things up in the BCB product line as follows.

  • Toughened BCB has been developed with 3X the elongation at some expense to CTE
  • A Dry film grade is being developed with thicknesses up to 100um
  • A positive-tone, aqueous developable product, BCB, 6505 is fully commercialized
  •  A BCB based temp bond adhesive, XP-130215,  for wafer thinning and 3D stacking is being sampled

I have compared the properties of a few of these new products to standard photo BCB 4000 below.

Property Cyclotene 3000/4000 Cyclotene 6505 (aq dev) Toughened BCB  BCB Dry Film
Cure temp (˚C) 210-250 210-250 210-250   200-250
Tg 350 350 350   250
Dk 2.7 3.2 2.7   2.6
CTE (ppm) 42 45 70   63
Tensile Strength (Mpa) 87 99 93   80
Elongation (%) 8 13 25   13
Residual stress 28 29 24   28
H2O uptake (%) 0.25 1.1 0.3   0.1

 

The PI community has not been standing still either. PIs always known for their high temp stability and their superior mechanical properties has had some catching up to do when it came to curing temperature amongst other properties.

HD Micro offers the following product lines.

C-4 flip chip RDL layers:

-        HD 4100 negative tone photo PI

-        HD8800 positive tone photo PBO

-        HD 8900 positive tone low cure temp photo PBO

2.5/3D Adhesives:

-        HD 3000 non photo temp adhesive

-        HD 7000 photo PI permanent adhesive

Stress Relief and Passivation Layers:

-        PI 2545 non photo wet etch PI

-        HD 8800 positive tone photo PBO

-        HD 8900 positive tone photo PBO low cure temp

Properties of these materials are compared below:

fig 1

Zeon

Zeon is introducing the new positive tone photo “olefin based” Zeocoat  CP 3010 designed to deliver a low cure temp, low stress coating. Below are the properties of the polymer determined after a 180 C cure.

Property Zeocoat CP3010 (cured at 180 C for 1 hr)
Water Abs (ppm)

(130 C;98%RH;100 hr)

1750
Mod (GPA) 2.9
CTE (ppm) 51
Stress (MPa) 23
Tensile Strength (MPa) 97
Tg ( C) 196
Dielectric constant (1MHz) 2.9
Leak current (A/cm2) @2 MV/cm 1.0 e -10
Breakdown Voltage (MV/cm) 6.5

 

For all the latest on 2.5/3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 212 A Little More Patience Required for 2.5/3D

Wednesday, October 8th, 2014

By Dr. Phil Garrou, Contributing Editor

There is an old proverb that states “All things Come to Those Who Wait.” It is exemplified by the French cartoon (below) showing a cat patiently waiting for a mouse to exit his hole in the wall. I personally am not the waiting type wanting to get things done ASAP but most civilizations look at patience as a virtue.

fig 1

We’ve discussed the leading edge before. The leading edge is where the money is made. So while you don’t want to be too early, you certainly don’t want to sit back and wait to see if something is going to happen and let others drain all the profit from that early period of introduction.

Now having said that, let me counter by saying that “All things don’t come to those who wait”. I waited for thin film  MCMs to take off in the 90’s and early 2000’s and they never did.  A lot of us gambled and in that case – lost. Life is a gamble !

TSV technology and 2.5/3D has had its own  dichotomy. We couldn’t sit back and allow others to get there first so we all anteed up our time and money without any assurance that there is big money to be made on this technology. Like the cat, we have been waiting (some more patiently than others) for 2.5/3D to enter HVM when in fact there has been no assurance that the mouse wasn’t going to exit from another wall (i.e another technological solution as happened in thin film MCMs).

Anyone who understood what TSV technology could bring to the party, knew that HVM and actually new product design itself could not expand until foundry technology was available (since TSV were/are clearly going in during chip fabrication) and memory stacks were available, since foundries don’t make DRAM. Of course it all has to be at the right price, but if its not even available, what matters the price?

In terms of foundries TSMC [see: IFTLE 122, “TSMC officially ready for 2.5D….”, ] was the first to announce and GlobalFoundries is not far behind [see; IFTLE 142,  “GlobalFoundries 2.5 / 3D at 20nm…” or IFTLE 164, “Semicon Taiwan contd: GlobalFoundries Manocha Interview”  ] so those at the leading edge can now design in 2.5D. But what about memory ??

While UMC [see: IFTLE 135, “UMC / SCP Memory on Logic…” and a few others have made noise about entering the 3D market space they appear to be significantly further behind.

The status of memory

Memory, as IFTLE has noted several times, has been slower coming.

The DRAM industry has been undergoing significant consolidation in the last few decades. The recent acquisition of Elpida by Micron has left 3 major players in the DRAM business as shown below.

DRAM Mkt Share of the Big 3 [Source: Gartner 2014] DRAM Mkt Share of the Big 3 [Source: Gartner 2014] 

Moving forward the main roadmaps for DRAM suppliers all address: (1) reduce power consumption, (2) satisfy bandwidth requirements and (3) satisfy density requirements , all while maintaining low cost.

With DDR architecture running into a brick wall the memory suppliers have been focusing on new architectures that will deliver lower power, higher bandwith memory solutions.  These include wide IO-2, HBM (high bandwidth memory) and HMC (hybrid memory cube).

Definition, standardization and scale up of these memory technologies has simply taken longer than any of us would have liked, but these are the new architectures what will take advantage of TSV stacking technology.

TSMC has recently compared the different memory architectures relative to DDR and one another  in terms of bandwidth vs power and price.

Memory Architectures vs bandwidth, power and price. [TSMC] Memory Architectures vs bandwidth, power and price. [TSMC]I compare the technologies below.

 

Memory Std

Bandwidth        (GBps)

Voltage

Standard

Applications

Wide IO 2

68

1.1

JESD 229-2

High end smart phones

HMC

160

1.2

HMC consortium

High end servers, networking, graphics

HBM

128 (gen 1) 256 (gen 2)

1.2

JESD235

High end graphics, networking and HPC

Comparison of New Memory Architectures

As we head into the fall of 2014 the last probably most important of the big 3 memory suppliers, Samsung,  has now announced production of TSV based memory stacks [see: IFTLE 209, “Samsung announces TSV based DDR4 ….” ].

So we are about to have HBM for graphics modules, wide IO-2 for mobile products and HMC for HPC and high end servers. Now there can be no more excuses.

Within the next 18 months, if we do not see product introductions announced,  2.5/3D will begin to fade away until it is only remembered as another one of the bad bets we made attempting to stay on the leading edge…

For all the latest on 2.5/3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 211 Semicon Taiwan part 2: Unimicron, Yole, Micron

Wednesday, October 1st, 2014

By Dr. Phil Garrou, Contributing Editor

Continuing our look at 2014 SEMICON Taiwan.

Unimicron

YH Chen of Unimicron addressed “Panel Level Embedded Substrate Technology.”

Unimicron puts forth a proposal that embedded packaging saves cost because it (a) decreases the substrates used,(b) decreases the area of HDI board needed, (c) better electrical performance due to the proximity of the chips.

Unimicron 1

 

Unimicron started embedded passives technology (EPS) in 2009 and moved to HVM in 2012. This is based on burying MLC (multilayer caps).

Buried chip technology called EAS has the following roadmap:

unimicron 2

They are also looking at embedded hea “slugs” to increase thermal performance.

Line Embedded technology (LE) uses lasers to creat fine fetures that are then plated up and CMPed to give L/s as low as 8/8um.

unimicron 3

In another cost reduction development project, they are looking at combining the non organic interposer and the organic substrate into what they call “flip chip embedded intrposer carrier” as shown below.

unimicron 4

Yole Developpement

Azemar of Yole Developpement looked at “Fan-out & Embedded Dies Technologies and market trends.”

Azemar explained again that 2 different approaches are developing for Embedded packages, i.e. FOWLP based on reconfigured molded wafers and embedded die based on PCB laminate materials and infrastructure.

Currently Nanium and StatsChipPAC hold > 80% of the FOWLP market though this is expected to change when TSMC fully enters the market with their InFo-WLP technology.

yole 1

A generic embedded die packaging flow is shown below.

yole 2

For embedded die packaging, a new supply chain is required since the die embedding will be done by the PCB manufacturer who is making the substrate.

AT&S appears to hold ~ 80% of the embedded de market. They initiated this space with the TDK DC_DC converter package but Yole reports very little HVM since then.

yole 3

Micron

At the CFO Executive Summit Strohbecke of Micron  looked at “Micron Technology and the Changing Dynamics of the Memory Semiconductor Industry: Their 2014 vs 2018 assessment of DRAM demand vs application shows an increase in mobile and server/networking at the expense of PC memory.

micron

 

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…