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IFTLE 207 IEEE ECTC part 2: Advances in Fan-out Packaging

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the “Fan Out” papers that were presented at the 2014 ECTC.

STATSChipPAC (SCP) and the totally encapsulated WLP

Tom Strothman from SCP presented an update on their fan-out technology to produce fully encapsulated WLPs. Strothman reminded us that the WLP was invented, patented and commercialized by Flip Chip Technologies (FCT) in 1998 when they released the “Ultra CSP”. Tom was part of that FCT team along with Pete Elenius.  I recall that well, since I was at Dow Chemical in those days working with FCT on the program with my team which included current industry veterans Boyd Rogers and Andy Strandjord.

Luu Nguyen, then at National Semi, and a licensee of the FCT technology  was the first to coat the backside of the WLP with a layer of molding compound both for protection and to enable laser marking.

SCP has now taken this to the next level by developing their eWLCS (an acronym I assume for Wafer Level Chip Scale)  which is the only WLP to offer protection on all sides of the package.

The process starts with a high volume manufacturing flow developed by STATS ChipPAC for fan-out products. In this manufacturing method the wafer is diced at the start of the process and then reconstituted into a standardized wafer (or panel) shape for the subsequent  process steps. The basic process flow for creating the reconstituted wafer is shown below. The singulated die are accurately placed face down onto the carrier with a pick and place tool. A compression molding process is used to encapsulate the die with mold compound while the active face of the die is protected. After curing the mold compound, the carrier and adhesive foil are removed in a de-bonding process resulting in a reconstituted wafer where the mold compound encapsulates all exposed silicon die surfaces.

After the reconstitution process, the reconstituted wafer is processed with conventional wafer level packaging techniques for the application and patterning of dielectric layers, thin film metals for redistribution and under bump metal, and solder bumps. In the final dicing operation a thin layer of mold compound, typically < 70um, is left on the side of the die as a protective layer as shown below.

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One would assume that the process flow shown above would have higher cost since there are additional steps required for reconstitution at the start of the flow. SCP contends that there are two key factors that offset the cost of the additional steps. 1) In the case of the 300mm reconstituted panel used here the cost is very competitive for silicon wafers with a diameter of 200mm and below. SCP claims the cost of processing a 300mm reconstituted panel is approximately 1.7x the cost of processing a 200mm silicon wafer in WLCSP, however the units per panel (wafer) increases by a factor of 2.3x, effectively offsetting the cost of reconstitution. 2) Since known good die can be selected at the start of the process, advanced devices that have a lower electrical yield can be tested in wafer form prior to the process. If the incoming wafer has a probe yield of 85%, then 15% more units per reconstituted panel can be processed to offset the cost of the reconstitution process.

Since the reconstituted panel size is no longer linked to the incoming silicon wafers size, the panel size can be increased over time and provide further cost reduction.

Because of the presence of molding compound, the RDL on these structures cannot use the typical PI, BCB or PBO dielectrics, but rather must use a as yet unnamed low temp cure material.

TCT (thermal cycle tsting) passes 500 cycles ( -4o to 125 C) and drop testing passes the JEDEC 30 drop requirement.

Siliconware (SPIL) panel fan-out packaging (P-FO)

Chang of SPIL discussed their efforts to commercialize he panel fan-out package concept  by combining  PCB, semiconductor back-end, semiconductor WLP and LCD Gen 2.5 glass processing technologies. This effort requires high accuracy die bonding and die shift compensation at film lamination, lower warpage sheet form film lamination, good copper trace plating uniformity control at large panel area and also precise photolithographic technique.

Known good die are reconstructed on the LCD Gen 2.5 (370X470mm) size glass carrier with adhesive temporary bonding material.

Processing issues are identified as warpage, die shift “coordinates compensation at lithography” and Cu plating uniformity.

They claim that warpage can be controlled to +/- 0.5mm after carrier debonding. They describe die shift compensation as a “compensable patterning method” which is not described but probably is similar to techniques recently described by Deca [see “Adaptive Patterning for Panelized Processing”]

Little detail is given on how they are going to achieve these requirements.

Nanium – eWLB Dielectric Selection

In eWLB technology  the reliability of the package is a balance of the capability of the different layers that constitutes the package in absorb shocks and mechanical stress from the different materials CTEs. In IC packaging interfaces, the dielectric material, plays a significant role absorbing thermal stress and mechanical shocks slowing down cracks propagation. A wide range of material classes has been considered including PBO, PI, nano-filled Phenol resin, BCB, Silicone, Epoxies, Siloxanes ,  Polynorbornenes and Acrylates. Fifty six56  dielectrics from seventeen manufacturers were compared based on physical, mechanical, thermal, electrical and chemical properties.

They found the most significant material properties are the elongation to break, the tensile strength and the Young’s modulus as they are an indicator of how a polymer will perform under mechanical stress caused by CTE mismatch between the die and the molding compound in thermal cycling and in mechanical shock drop tests.

A PI precursors formulation was selected based on its low curing temperature compatible with eWLB FO-WLP products and processing temperature restrictions. The unidentified PI precursor formulation is NMP/NEP solvent free. It is compatible with copper and all the other chemicals used in production process like solvents, bases and acids. Thus, the PI precursor formulation was selected to be used as buffer layer and also as RDL top layer.

Use of this dielectric reportedly allow  NANIUM to exceed 1,000 cycles in component level based Temperature Cycling Test (TCT -55ºC to 125°C) and 500 to 1,000 cycles, in board-level based Temperature Cycling on Board Test (TCoB -40ºC to 125 °C) according IPC-9701 and JEDEC JESD22-B111 Drop Testing.

Google / Novartis – Wearable electronics for diabetics ?? 

Google and Novartis, announced that  they will create a smart contact lens that contains a low power microchip and an almost invisible, hair-thin electronic circuit. The lens can measure diabetics’ blood sugar levels directly from tear fluid on the surface of the eyeball. The system sends data to a mobile device to keep the individual informed.

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The Mountain View CA Google team involved in this program is the stealth  “Google X” group which focuses on “finding new solutions to big global problems” in healthcare and other areas.

For all the latest on 2.5/3DIC and advanced packaging, stay linked to IFTLE…

4 Responses to “IFTLE 207 IEEE ECTC part 2: Advances in Fan-out Packaging”

  1. Klaus Ruhmer Says:

    The mentioned die shifts can be a significant challenge. A novel closed loop – feed forward approach by Rudolph Technologies which measures die location (Rudolph NSX) and feeds the data forward to the lithography stepper (Rudolph JetStep) is a great solution to overcome die-shift related overlay issues.
    Klaus Ruhmer
    Rudolph Technologies, Inc.

  2. Blog review September 8, 2014 | Semiconductor Manufacturing & Design Community Says:

    [...] Garrou takes a look at some of the “Fan Out” papers that were presented at the 2014 ECTC, focusing on STATSChipPAC (SCP) and the totally encapsulated WLP, Siliconware (SPIL) panel fan-out [...]

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