IFTLE 199 Omnivision Roadmaps 3D stacking for CMOS Image Sensors; IC Insights Details Trends Shaping the IC Industry
By Dr. Phil Garrou, Contributing Editor
Since Toshiba started using backside TSV in 2008 we have been anticipating stacking of separate functions in true 3DIC fashion. Last summer, Sony announced such a structure. [link 1]
Recently, at the image sensors conference in London, Dr. Howard Rhodes, CTO of Omnivision, gave an keynote entitled “The Future of CMOS Imaging” where he expounded on the advantages of stacking and the separation of the imaging function from the logic function.
Of special interest are Rhodes comments on “stacked CIS” which he calls “replacing the BSI Si substrate with logic.” Their roadmap shows Omnivision moving from wafer bonding with simple oxide bonding to “hybrid bond stacking with simultaneous bonding of oxide and Cu contacts to 3 wafer stacking where sensors, ISP and memory are fabricated separately and stacked.
Longtime readers of IFTLE will recognize that Gen 1 “Oxide-oxide” bonding is the technology Sony licensed from Ziptronix in 2011 [link].
“Hybrid bonding” is the term commonly used to describe the patented Ziptronix DBI process where oxide and copper (or other metal) bonding occurs simultaneously [link], so one should expect to see more Ziptronix licensing in the future.
IFTLE would guess that there will be further licensing in Ziptronix future.
At the recent SST ConFab in Las Vegas Bill McClean shared his annual report on “Major trends shaping the future IC Industry.” IC insights reports that recent growth in the IC industry has been mainly in memory.
For the first time in 2013, communication surpassed computers in terms of market share.
Fabless sales are now 29% of total IC sales with the US is holding its ~70% market share of fabless market sales which it has had since 2010.
The bulk of capex spending is being done by the major players, i.e. the ones who appear set to move forward to lower nodes (1-7 in the chart below).
Over the last two decades, the percentage of capex being spent by the top 5 has steadily increased to its current 70% with the big three of Samsung, Intel and TSMC being responsible for over 50%.
A look at capital spending by region shows Japan and Europe falling for behind with a combined sub 10%.
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