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IFTLE 193 SEMI Singapore Part 2: SPTS and STATSChipPAC

By Dr. Phil Garrou

At the recent 2.5/3DIC Forum at SEMI Singapore Dr. Surya Bhattacharya, Director of Industry Development (TSV) at, A*STAR Institute of Microelectronics chaired the day long session looking at the state of TSV technology. Let’s take a look at some of these presentations.


SPTS updated attendees on their endpoint controlled “via reveal” etch process. As we know, via reveal involves the following process sequence:


The SPTS Rapier module has their “ReViaTM” in-situ end-point detection technology which they claim increases throughput and yield.



The SCP presentation looked at “2.5/3D Integration: Moores Law and Beyond.” One message here is that 2.5/3D is not a cure all. As we have seen SCP present in the past, they conclude (and IFTLE concurs) that the right packaging solution must be chosen based on the requirements of the unique opportunity. We have seen the figure below before, but it is worth showing it again.


For instance, comparing 2.5D to an eWLB solution:


SCP reiterated that they see their position in the infrastructure as mid end and back end of line.


Their work with UMC which was initiated in 2012 has taken structures such as wide IO memory on Aps processors through reliability with positive results.


SCP has demonstrated MEOL (mid end of line) and BEOL process capability for 2.5/3D TSV with hand-off between foundry and OSATs.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

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