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Archive for April, 2014

IFTLE 190 TSMC Focus on Packaging; Samsung Licenses “3D” to GF; More on IBM and the Cloud

Tuesday, April 29th, 2014

TSMC Packaging Plans

Digitimes reports that  TSMC plans to ramp IC packaging revenues to US $1 billion in 2015 and $2B in 2016 [link] . Based on this roadmap, TSMC would  become the 3rd leading  packaging company in Taiwan by 2016, trailing  only ASE and SPIL.

At the TSMC NA Technology Symposium April 222nd in San Jose,  TSMC described a wide range of  packaging offerings including  an integrated fan-out wafer level packaging (InFO-WLP) process which will start production by the end of the year and  an InFO PoP configuration which will enable stacking a wire-bonded multi-die package on top of an InFO-WLP. They also have a more standard WLCSP ( Wafer-level Chip Scale Package) that  will support devices with up to 800 pins.

Samsung licenses 3D chip manufacturing tech to GlobalFoundries

As I headed out of town to spend Easter with the grandkids last week, my phone pinged me with the following Reuters headline. “Samsung licenses 3D chip manufacturing tech to GlobalFoundries to win more orders” [link]

“Wow that’s great” I thought as I boarded the plane. A few hours later, now in Houston, I turned on my phone and quickly found the article. Down in paragraph three we find that they call their 3D technology “finFET.” Nothing in this article was incorrect and it’s not like we are the only community who are allowed to use the term 3D, but it sure does make things confusing. Recall the EE Times headline in 2011 “TSMC May Beat Intel to 3D Chips” where 3DIC was unknowingly being compared to FinFet. [See IFTLE 62, “3D and Interposers – Nomenclature confusion; Equipment Market Shift to Pkging Continues”]

Glad to report that EE Times learned its lesson and this time came out with a more appropriate headline than Reuters namely “Samsung, Globalfoundries Prep 14nm Process” [link]

 

More Info on IBM and the Cloud

IBM just reported its lowest quarterly revenue in 5 years on Wednesday as Reuters reports “…the company struggles with falling demand for its storage and server products.”[link]

We have recently discussed IBM semi business being for sale and their proactive move into the “cloud” space [ see “IBM Continues to evolve: Semi business up for sale, moving into the clouds”]

Revenue from their hardware business, which includes servers and systems storage, felled 23 percent to $2.4 billion. IBM warned that the hardware business may continue to face issues with their CFO commenting, “As we look to the balance of 2014, …our overall revenue growth will be impacted by the challenges in our hardware business.”

IBM has also lost its position as number two software make behind Microsoft Corp. with Oracle recently claiming that position.

IBM

As IFTLE has told you, IBM looks like they are betting the farm on cloud computing which allows their customers to stop using (and replacing) servers by moving to remote data centers run by 3rd party companies. They have recently bought two companies to expand their cloud business, Silverpop, a developer of cloud-based marketing software, and cloud-based database software startup Cloudant.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 189 IMAPS DPC Part 3: FCI, GF/Amkor; Corning; Namics

Tuesday, April 22nd, 2014

By Dr. Phil Garrou, Contributing Editor

Flip Chip Int (FCI)

FCI and Suss Microtec examined the use of lasers in the manufacturing of WLP.

Commercial dielectric via formation today used in WLCSP, RDL and flip-chip products typically rely on standard photolithography processing using stepper and 1x aligner equipment and processes.  Interest in using laser via drilling (ablation) centers on the following reasons.

- Reduced via dimensions

-  Simplified process flow

- Reduced process time

- Cost reduction

- Enable a broader range of  dielectric materials (i.e., non photo dielectrics and mold compound)

- Eliminate organic solvents used in many pholithography process

FCI 1With PBO via dimensions as small as 7.3um are demonstrated on PBO with an application desired sidewall angle around 60 degrees. Sidewall angles can be adjusted by changing the laser fluence and other settings.

- Higher fluence: Steeper wall-angle

- Lower fluence: Shallow wall-angle

Underlying metals (> ~1µm) can be used as a laser stop for via formation. By controlling the fluence and other settings the process has the ability to also stop at a certain depth in the dielectric without a metal backstop.

Since laser via ablation can produce smaller via dimensions compared to standard photolithography methods, using a laser via ablation technology can improve the design rules for next generation RDL layouts.  In addition, the ability to utilize non-photosensitive organic dielectrics can enable better mechanical and thermal properties as the bump diameter and pitch shrink, improving end product reliability.

Global Foundries / Amkor / Open SIlicon

GF, Amkor and Open Silicon described their 2.5D ARM dual core product demonstrator which consists of 2 ARM die on a high density  silicon interposer. A schematic of the module and he process flow are shown below . It was noted that “…extensive UF material development was needed”  for the u-bump pitches that were used. A cumulative yield of 93.7% was achieved.

GF 1-1

They used the following assembly flow:

GF 2

Corning

Corning is beginning to show results of the multiple glass interposer programs they have instituted at sites such as RTI in RTP NC, GaTech and ITRI. One interesting proposal from Corning is that starting with 100um glass substrates should eliminate the need for backside grinding  for via reveal . The 100um “Willow glass” with TSV is temp bonded to another glass layer  and the TSV are filled . The interposer “panel” or wafer is then removed from the temp bonding substrate.  It will be interesting to learn exactly how that is done (both the metallization and the release).

Work with RTI is showing the filled TGV can survive ( defined as less than 15% increase in initial resistance) greater than  700 thermal cycles of -55 to 125 ˚C and 20 x 20 arrays of TSV on 100um pitch are showing > 99.9% yield.  The RTI team has also begun to show assembly of chip to glass using copper pillar bump technology.

Namics

Namics is developing their underfill products to meet the following roadmap for FC BGA and FC CSP.

Namics 1

Underfill materials can be classified as follows:

namics 3

Their FEA modeling shows that Cu pillar and lead free bumps require a higher Tg underfill to protect from bump fracture during TCT, however low Tg may can assist with warpage, delamination and failure.

Modeling also showed that stress on low K of the IC is increased when using fillers that show filler separation (settling).

Underfill void elimination can be reduced by either using  vacuum assisted CUF  or curing in pressure oven.

namics 3 Untitled

For all the latest in 3DIC and advanced packaging technology, stay linked to IFTLE…

 

 

IFTLE 188 IMAPS Device Packaging Conf Part 2: AMD, SCP

Monday, April 14th, 2014

Continuing our look at the recent IMAPS DPC with several key presentations.

AMD

AMD’s keynote presentation by Bryan Black updated us on their thoughts about “Die Stacking and High Bandwidth Memory.” Black stated that “…while die stacking is catching on in FPGAs, Power Devices, and MEMs, there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!”

As we have discussed on IFTLE many times, Black agrees that future nodes will NO LONGER bring down transistor costs which has been a longstanding premise of Moore’s Law.

AMD 1

Die Stacking Motivation

  • Process complexity is increasing and yield is dropping as mask count increases
  • Large die sizes will continue to have yield challenges

AMD 2

Black adds that die partitioning is challenging and there is significant microarchitectural research to be done since the buss to connect partitioned chips is very complex.

As we heard from Hynix at the RTI ASIP conference in December 2013 [see “AMD and Hynix announce joint development of HBM memory stacks,” the first generation of Hynix high bandwidth memory is now sampling.]

AMD 3

This results in a 3X improvement in bandwidth per Watt.

AMD 4

Black envisions silicon interposers replacing SoC for high end platforms in the future.

AMD 5

Black announced that AMD AND Hynix were looking for partners to begin immediate development of such products.

STATSChipPAC (SCP)

In an attempt to expand the usage of their eWLB technology, SCP announced FlexLineTM as a “breakthrough manufacturing method for Wafer level packaging”.

Tom Strothmann of SCP pointed out that OSATS have traditionally been forced to use wafer processing equipment sets for both 200 and 300mm wafers, that typically have higher cost and capability than needed.

Currently, separate equipment sets are required to manufacture WLCSP from 200 or 300mm wafers whereas the FlexLine process allows them to be manufactured on the same equipment set.

The SCP FlexLine process flow is based on the SCP commercial eWLB FO-WLP process [ see IFTLE 124, “Status and the Future of eWLB…”]. Single and multi die fan-out package solutions have been in HVM since 2009 with more than 500MM units shipped. SCP eWLB have passed all standard component and board level reliability tests.

FlexLine uses eWLB technology to dice and reconstitute incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size.

fig 2 SCP

The following 2D/2.5D products can be fabricated on the same FlexLine using a  standard process flow.

fig 3 SCP

Process Flow:

- Dice the wafer to dimensions slightly larger than nominal die size

- Process through reconstitution, redistribution and ball drop

- singulate removing the mold compound from the side of the die and reducing the die size back to the nominal size

To create an encapsulated WLCSP (eWLCSP):

- Dice the wafer at nominal die size

- Process through reconstitution, redistribution and ball drop

-Final singulation is done larger than the die size, leaving a protective layer of mold compound on the sides of the die

- The end product here  is a e-WLCSP that cannot be made with conventional WLCSP processes

Strothmann indicates that SCP COO studies conclude that the added cost of reconstitution is offset by the larger panel size that is processed. CTO BJ Han adds “…with FlexLine we are able to help our customers achieve at least a 15-30% cost reduction using the optimum design requirements for their WLCSP devices.”

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

 

IFTLE 187 More IBM rumors; Altera FPGAs, IBS Addresses Transistor Costs, ASE / Inotera 3DIC JV

Monday, April 7th, 2014

IBM Semiconductor

According to the Wall Street Journal GlobalFoundries (GF) “…has emerged as the leading candidate to buy IBMs semiconductor operations.” [link]  According to these reports IBM who initially asked for $2B has met with TSMC, Intel and GF. The reports continues that  and that TSMC has dropped out of the bidding which exceeded $1B but appears contingent on how much intellectual property IBM includes.

IFTLE readers already knew that GF was the lead candidate [ see “IBM Continues to evolve: Semi business up for sale, moving into the clouds”]. Maybe the WSJ is reading IFTLE ??

Intel / Altera / TSMC

Recent reports indicate that Altera had expanded their foundry deal with Intel to include “multi-die” devices that combine Altera’s Stratix 10 FPGAs and SoCs with DRAM, SRAM, ASICs, processors, and analog chips in a single package.” [link]

This announcement left some in the industry confused.

Let’s review some background…

Recall in March 2012 Altera announced that they were working with TSMC on 2.5D FPGA program (much like their already commercial competitor Xilinx). [“Altera and TSMC Jointly Develop World’s First Heterogeneous 3D IC Test Vehicle Using CoWoSTM Process”]

Then in Feb 2013 Altera announced a foundry agreement with Intel to access their 14nm technology for FPGA production, probably meaning no need for 2.5D.

[see IFTLE 170, “GIT Workshop Debates Substrate Impact on 2.5/3DIC Costs; Altera 2.5D” ]

…but then, in Feb 2014, Intel announced the 14nm technology program was being postponed to 4Q2014/1Q215  [“Intel postponed Broadwell availability to 4Q14”].

…and then there were reports March 5th 2014 that Altera was “… expected to have TSMC fabricate its next-generation FPGA chips using TSMC’s 16nm FinFET+ process, instead of producing the chips using Intel’s 14nm tri-gate transistor technology”

So, I hope that is now clear (tongue-in-cheek) …

IBS

Those of you that stay linked to IFTLE know that I have been quoting Handel Jones of IBS for years (literally since 2009) since his analysis of what is happening to the economic infrastructure Re: Moore’s Law makes the most sense of anyone out there. The article he just wrote for EE Times, “FinFETs Not the Best Silicon Road” should be of interest to us all.

His premise is that semiconductor industry growth has historically depended on a reduction in cost per transistor but next-generation chips will not deliver this cost reduction. While next-generation 20nm bulk CMOS and 14nm FinFET process will deliver smaller transistors they will have a higher cost per gate than today’s 28nm bulk CMOS.

IBS 1

Cost will remain higher even as the processes mature.  IBS predicts that the traditional cross-over point for the newer generation technology will not happen  (point at which newer not becomes cheaper, per transistor, than older node. The cost per gate for 28nm bulk CMOS will be much lower than FinFETs even in the fourth quarter of 2017. A similar pattern will occur for 20nm bulk CMOS in 2018 or 2019 when depreciation costs decline.

IBS 2

Jones indicates that the 20nm node issues include:

- difficulty achieving low leakage due to challenges in controlling doping uniformity

- line edge roughness

- the need for double patterning

The 16/14nm FinFET node:

- uses the same interconnect structure as 20nm, so the chip area is only 8-10% smaller than 20nm

- faces yield issues related to stress control, overlay, and factors related to the step coverage and process uniformity of 3D structures.

Jones concludes that “..FinFETs can be used for high-performance or ultra-dense designs but are not cost effective in mainstream semiconductors “

ASE, Inotera reportedly to set up 3D IC packaging joint venture

Digitimes has reported that ASE and Inotera are reportedly setting up 3D IC packaging joint venture for handling TSV 3D IC packaging. ASE and Inotera are expected to finalize the deal soon, said the sources, adding that the joint venture is likely to be set up either at a Inotera’s idle plant or at a ASE plant in Chungli, Taiwan.

Initial production goals are reportedly 10,000 3D IC chips a month,  and should include Aps (application processors) and mobile RAM chips.

DIgitimes sources add that they expect the JV  to compete with TSMC in the 3DIC packaging sector.

Inotera, incorporated in 2003, is a joint venture between Nanya Tech (an affiliate of the Formosa Plastics Group) and Micron.

Inotera has two 300mm fabs with a combined capacity of approximately 120 thousand wafer starts per month providing 300mm DRAM foundry services. According to the supply agreement between Inotera and Micron Technology, Inotera sells substantially all of its manufacturing output to Micron.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…