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Archive for December, 2013

IFTLE 173 IMAPS 2013 – Materials Advances; Namics, Towa, Dow; Wiley VCH reading Vol. 3 of 3D Integration Handbook

Wednesday, December 18th, 2013

The IMAPS National meeting was recently held in Orlando, FL. Let’s first take a look at some of the materials papers that were presented.

Namics 

Namics presented their latest data on available underfill solutions for 2.5/3DIC. Below we see several opportunities for epoxy underfill materials.

Namics 1

Vacuum underfilling is replacing CUF due to decreased voiding which improves reliability. Underfill must have a high enough Tg to insure the modulus is high enough to protect bumps during thermal cycling but low enough not to crack the die.

Namics proposes that in the near future it might be possible for substrate suppliers to apply a B staged underfill prior to shipping. The customer would then perform a thermo-compression bond.

Despite the obvious benefits, the drawbacks of both NCP (non conductive paste) and NCF (non conductive film) at present include required additional capital, cost more and have a longer bonding time.

Application methods for Various Underfill Solutions Application methods for Various Underfill Solutions

Towa – Compression Molding for High End Packaging Solutions

Traditional transfer molding  has been challenged to mold 2.5/3D stacked die structures since these structures have limited space for resin flow. It is also difficult to transfer mold large wafer or panel substrates.

Compression molding was developed to mold packages with minimum resin flow. The blue layer, in the figure below , is a release film which is sucked down flat to the mold. A vacuum is subsequently pulled to remove air, gas and moisture from the cavity and molding cmpd.

Towa 1

Dow Chemical – toughened BCB

BCB has been commercially used by the packaging community for more than 20 years. Although it has various superior properties such as low curing temp, low water absorption and low dielectric constant, being a thermoset resin, toughness and elongation are not one of them.  A toughened BCB has been a “holy grail” in the BCB user community.

A new toughened BCB product has now been described by Dow. Comparative properties are shown below. As one can see most properties have been maintained while elongation has been improved 3X and shows a 2X increase in fracture toughness from 0.3 to 0.4 to 0.6 – 0.9 MPa m1/2  vs standard BCB.

dow 1

A cross section of a via in this toughened BCB is shown below.

dow 2

Volume 3 of 3D Integration Handbook being readied

It was 2008 when the Handbook of 3D Integration was published by Wiley VCH.  Since then it has been the most referenced 3D treatis on the market. Much has happened since 2008 and we, the editors, felt that rather than update the first two volumes , we would rather issue further volumes updating some chapters and adding others as required and Wiley VCH agreed.

Volume 3, due to be published 1st quarter of 2014 will be focused on processing and will include chapters on 2.5D interposers, TSV formation, bond/debond, thin, reveal and backside processing, reliability and metrology. Authors in this volume, in addition to the editors, include  Eric Beyne (IMEC),  (EVG);  Hiroaki Ikeda (ASET); James Lu (RPI); Thorsten Matthias (EVG); Rama Pulligadda (Brewer); Sesh Ramaswami (Applied Materials); Fred Roozeboom (TNO); Rao Tummala (GaTech); Larry Smith (Sematech); Doug Yu (TSMC).

wiley cover

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 172 Sony TSV Stacked CMOS Image Sensors Finally Arrive in 2013

Monday, December 9th, 2013

By Dr. Phil Garrou

Many of us can recall 2008 when Toshiba commercialized the first CMOS image sensor with TSV last /backside. We called these the first 3DIC products, when in reality they were only 1 layer devices.  More recently we have discussed Sony’s plans to release CMOS image sensors where the circuitry and sensors are fabricated on separate wafers and joined by TSV – i.e. true 3DIC structures. [see IFTLE 112,”TSMC Staffing up for 2.5/3D Expansion ; Semi 3D Standards; Sony shows off 3D stacked Image Sensors” and IFTLE  137, “CMOS Image Sensor market update”]

Somehow IFTLE missed detailing the actual product technology release of the Sony ISX014 (link)  at the ISSCC earlier in the year. This is important enough in terms of 3DIC product introductions that we will cover it now.

The Sony ISX014 8MP sensor features 1.12um pixels and integrated high speed ISP.The pixel layer and logic layer part are manufactured as separate chips and stacked by using TSVs. Previously the pixel and logic circuit of Sony’s back side  illuminated (BSI) CMOS image sensor were formed during the same fabrication process. This is compared below.

SOny 1

Actual layers are shown below:

Sony 2

Using separate pixel and logic layers allows the use an optimal process technology for each separate layer. Sony fabricated the pixel chip and logic chip using 90nm and 65nm process technologies, respectively. Stacking the chips, reduced chip area by 30%, compared with the previous image sensor made using 90nm process technology.

TSVs are used connect the row drivers on the pixel chip with the row decoders on the logic chip and connect the comparators on the pixel chip and the counters on the logic chip. TSVs are formed in areas to reduce the influence of noise.  For example, comparators are arranged on the pixel chip, which can be manufactured by using Sony’s matured process technology, rather than on the logic chip.

The stacked vs conventional technologies are compared below:

Sony 3

Since the logic chip can be manufactured at Si foundries, Sony does not have to invest in advanced logic process technologies.

Sony is in volume production of the new CMOS image sensor for its smartphone, other companies’ tablet computers, etc. The size, pixel count and pixel pitch of the sensor are 1/4 inch, 8.08 million and 1.12μm, respectively. Characteristics of the CMOS device are shown below:

sony 4

Sony has not disclosed details on TSV processing. The total number of TSVs is a few thousand. The following figure shows the stacked chips cross-section.The insulators of the upper and lower chips are attached together. It seems that TSVs are formed later to connect the circuit layers of the chips. IFTLE assumes they are using the Ziptronics oxide bonding technology that they licensed previously [ see IFTLE 65, “Samsung’s 32GB RDIMM DDR3, GLOBALFOUNDRIES Packaging Alliance, Ziptronix Licensing News”.

sony 5 X sect

A recent cross section produced by chipworks helps us understand the interlayer connections done with 6um pitch TSV [link].

sony 6 chipworks

IFTLE would expect other CIS manufacturers to move in this direction shortly.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………………………….

Coming soon:

- An end of year update from Lester the Lightbulb         – more on IMAPS 2013

- more on the GIT Interposer Workshop                           – coverage of IWLPC

- more on IEEE 3DIC                                                              – coverage of RTI’s 3D ASIP

- Christmas coverage of Hannah and Madeline

 

IFTLE 171 Semicon Taiwan Part 3: Disco, Namics, Amkor

Monday, December 2nd, 2013

The last of our looks at September 2013′s Semicon Taiwan.

Disco

Disco claims to have 73%of the edge trim business and 90% of the back grinding business.

Disco offers trimming before or after bonding as shown below. Trimming after bonding shows faster blade wear and lower throughput. Trimming before bonding requires additional cleaning before bonding.

Disco trimming

Lowering the TTV (total thickness  variation) of temp bonding materials improves the TTV of the thinned silicon wafer. One option is to surface planarize the temp bonding material.

PLANAR

Cleanliness during the grind and CMP operations can be handled by integrated grind / CMP / clean units.

grind - polish

Disco offers both Blade and Laser Dicing.

dicing

Namics

Namics gave an update on CUF underfills for 2.5/3DIC. The Namics roadmap for capillary underfill is shown below.

semi CUF

Only fine filler underfills can be used with TSV stacked packages. Higher filler loadings are needed to reduce filler CTE.

thermal load

Higher thermal conductivity CUF can be made by increasing the filler content.

filler load

Vacuum assisted process or pressure assisted process can both be used to decrease voiding in CUF.

vacum cuff

Amkor

Choon Lee of Amkor gave a presentation on “From Advanced Packaging to 2.5D/3D.”

Interestingly, Lee predicted a silicon interposer cost of 2.7-4$/cm sq (100 sq mm) and expectations of organic interposer costs at 50% cost reduction.

Lee showed the following example of converting a silicon interposer to PCB.

Amkor1

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.