IFTLE 169 EMPC – Grenoble part 3: Fine Pitch RDL; Handling Ultra-thin Die; Backside Passivation as Stress Compensation
Leti / ST Micro – Interposer Fine Pitch RDL
Passive interposers redistribute the electrical lines from the attached upper dies down to the organic substrate through μPillars, RDL, TSVs and solder bumps, thus somehow acting as a pitch adapter between dies and substrate.
Backside RDL on a passive interposer can be created by either damascene integration or “conventional” integration as shown in the figure below.
Damascene approach mainly consists in full wafer copper plating over etched trenches followed by a CMP, allowing to retrieve at the end, a fully planarized surface. This integration allows an easy access to sub-micron line/space widths but at a higher cost, mainly due to CMP steps.
Leti / ST Micro have investigated investigate the minimum pitch that could be achieved with the conventional approach. Under their conditions they were able to achieve 8um l/s with high uniformity and reproducibility.
BESI/IMEC – Handling Ultra-thin Die
The use of ultra thin die (thickness less than 50um) requires specially designed handling solutions due to their fragility and flexibility.
BESI and IMEC have examined several tape types (UV vs thermal release), ejection systems, die size (5 x 5mm; 40um thick) and bump configurations.Click to view full screen.
They also examined both face up and face down to the wafer tape:
Their conclusions include: (1) proper dice/grind and stress relief needed to maximize die strength; (2) some UV tapes resulted in residues; (3) thermal release tapes gave larger process window; (4) stable and reliable picking of ultra-thin die can be achieved with throughputs greater than 3000 units per hour using several different hardware, maerial, process combinations.
SPTS – Low Temp Via Reveal Passivation with Stress Compensation
2.5 and 3DIC wafers require backside processing including thinning to reveal the TSV, passivation, RDL and creation of copper pillar connections. Before the wafer reveal process CMOS devices are usually temp bonded to carriers (Si or glass) and thinned to ca. 50um. The temperature stability of the temporary bonding adhesive sets a limit on the upper temp of subsequent processing steps. The current goal for this temperature would be ca. 190 C.
The backside passivation also serves to maintain the bow of the thinned wafers to a manageable level (ca. ~ 10mm) to allow subsequent processing steps. Full thickness 300mm wafers (770um) typically have incoming bow in the range of 100 – 200um. If thinned to 50um and released from the carrier the 300mm wafer would show a bow of several cm making them unprocessable and potentially lead to cracking after debond. Backside passivation stress can be tailored to compensate for the incoming wafer bow. CMOS cu/low-K wafers usually show tensile stress and thus backside stresses must be net tensile to compensate.
Compressively stressed SiN films generally give the best diffusion barrier properties. For the via reveal passivation stack compressive SiN with stress of – 100 MPa was used.
SiO films deposited using TEOS based chemistry is tunable from -200 to +200 MPa, but are must be taken since tensile SiO has a limited thickness cracking threshold.
TEOS Cracking Threshold (left) and SiN Electrical Characteristics
The final solution was to develop a 190 C SiN film with a tensile stress of +200 MPa and a cracking threshold of 7um (deposited onto compressive SiN barrier).
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Hope to see you all at this years RTI ASIP. It is the 10th Anniversary of this 3D focused meeting.