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Archive for July, 2013

IFTLE 156 2013 ConFab part 1 Sony, IBM, TI, SCP

Sunday, July 28th, 2013

Those of you that are readers of SST know from the editorials and blogs of Editor Pete Singer that the ConFab is Solid State Technology’s annual conference and networking event. This year, it was held in June 23-26 in Las Vegas.  The overall theme of this year’s conference is “Filling the fabs of the future.” IFTLE put together two sessions on packaging  which were jointly sponsored by IEEE CPMT and ConFab.

The most significant packaging announcement from the ConFab was SPIL announcing that they have put dual damascene in place and are ready to start supplying high-density interposers to the industry.

Sony CMOS Image Sensor 3D Stacking

Fellow bearded blogger Dick James of Chipworks, in his presentation “Inside Today’s Hot Products” showed some great X sections of the Sony IMX135 13 Mpixel CMOS Image sensor. One of the first stacked image sensors it consists of a 90nm back illuminated sensor bonded F2F with a 65nm image processor.

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IBM Orthogonal Scaling

Subu Iyer, IBM Fellow, lectured on his theme of “orthogonal scaling.” His premise is that classical silicon scaling is saturating and we need orthogonal approaches to “scale all aspects of the system including footprint and power.” Subu sees scaling continuing down to the 7nm node, but  “the cost per transistor has begun to saturate.”

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He predicts that the next component of Advanced System Integration will be 3D Integration:

- large interposer platform for heterogeneous integration

- Die Stacking

- stacking of logic die (high and moderate power)

- stacking of memory die (low power)

- Wafer level stacking

His example of stacked memory is the Micron IBM program on stacked memory:

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TI Thins Down Packaging

Devan Iyer, worldwide Dir. of Packaging for TI showed the thickness progression from the 1.75mm SOIC to the 0.075mm PicoStar-2G

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Iyer points out that while Package families are  proliferating, each package type has a “sweet spot” combination of cost, performance, form factor and reliability, driven by:

•Cost

•Electrical speed, power distribution and noise immunity

•Power dissipation

•Thickness, weight, PCB area consumption

•Board level reliability (BLR, drop)

•Environmental reliability

•Technical maturity vs. risk in high-volume manufacturing

•Testability

•Compatibility with Si process

STATS

Anderson of STATSChipPAC  points to smartphones and tablets driving our industry right now.

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For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.

IFTLE 155 2013 IEEE ECTC Part 2 Temporary Bonding

Sunday, July 21st, 2013

Continuing our look at key presentations from the 2013 IEEE ECTC Conference.

IMEC and Brewer Science reported on the “Integration and Manufacturing Aspects of Moving from  Waferbond HT 10.10  to ZoneBOND in Temporary Wafer Bonding.” Temporary wafer bonding has become a key element in the emergence of 3D Stacked IC technologies. In the past, approaches such as IMEC’s have relied on the “thermal slide process” to debond the thinned wafer from the carrier.  There was a desire to move away from this process for several reasons including: (1) stresses that are generated can cause cracks in thinned wafers, especially those containing TSV; (2) slide debond normally conducted > 200 C which accelerates solder diffusion; (3) cannot slide debond if already on dicing frame since no dicing tapes can take temps > 200 C.  This led to the development of the ZoneBOND process which has been described previously.

Integration Changes Required for the ZoneBOND process

In the standard process sequence edge trimming is done to the device wafer prior to temporary bonding. If this is done in the ZoneBOND process, the find that adhesive is trapped in the trimmed region of the wafer and clogs the grinding wheel during backside thinning.

A new integration scheme is proposed where edge trimming occurs after the bonding step as shown below.

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Debonding is performed at room temperature in a SUSS DB12T debonder. First, a wet edge preparation is required in order to eliminate the high adhesion area of the adhesive layer between the 2 substrates. Then, the thin device wafer still bonded to the carrier is laminated onto a dicing tape on frame. Next, the room temperature peel off debonding separates the thin wafer from the carrier while the thin wafer is still on tape and on frame. A final cleaning step on tape is performed to remove adhesive residues from the device wafer.

CEA Leti reported on their comparison between the  “WSS and ZoneBond Temporary Bonding Techniques.”

The ZoneBOND technique requires silicon carriers that are treated with an antistick layer with an edge exclusion to ensure the adhesion. Temporary glue can be deposited either on the device, either on the carrier. Bonding is achieved under elevated temperature and separation requires a specific soaking of the bonded pairs to preliminary remove the adhesive from the edges.

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The WSS system requires transparent carriers as the temporary adhesive is cured after bonding by UV exposure. Separation is enabled by a laser exposure which modifies a sensitive layer (named LTHC for Light to Heat Conversion) that has been deposited before bonding on the carrier.

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Pros and cons of the processes are given in the attached table.

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For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.

IFTLE 154 ICEP part 2: Thinning Effects on DRAM memory retention and More

Thursday, July 11th, 2013

Continuing our look at the Osaka ICEP conference held in April 2013.

ASET and Tohoku Univ

ASET and Tohoku Univ reported on the effects of thinning on DRAM and CMOS device characteristics. Basically the thinner the chip becomes, the more likely it is that mechanical stress will alter the device characteristics and that ionic impurities will contaminate the transistors.

Perhaps most importantly they thinned a 65nm NMOS DRAM to 200 um by mechanical grinding and then further thinned down to 30um by stress free CMP. They then examined the data retention time of the chip vs thickness (see below). Data retention of the 30um thick device was ½ of that of the 200um device!

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DNP

Dai Nippon Printing and AIST have examined the fabrication of interposers on 300 mm wafers and attempted to reduce cost.

500um thick interposers with 50um diameter TSV were fabricated on 300 mm wafers, insulted with SiO2 (TEOS based PECVD), filled with ECD Cu and the Cu CMP’ed to remove overburden (50-100um). They note that it was “difficult to form void free TSV due to he high aspect ratio (10:1).  Backside RDL was done with PBO dielectric (8um deposited and 50% shrinkage). They conclude that this process flow eliminates the need for wafer support since the 500um thinned wafers can be directly processed without support.

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ITRI

ITRI described their studies on the assembly of 3D stacked chip with 30um pitch microbump interconnects using both non conductive paste (NCP) and anisotropic conductive film (ACF).

The bump structure for NCP bonding is shown below. Cu/Ni/Sn solder micro bumps are connected to Cu/Ni/AU micro bumps. For ACF Cu/Ni/AU micro bumps are joined to Cu/Ni/Au micro bumps.

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The NCP was an epoxy thermoset. Properties of NCP and ACF are shown below.

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The NCP assembled chip stack passed 1000 cycles of TCT and 1000 hrs of HTS without any failures. The ACF assembled stacks all failed after 85/85 testing for 100 hrs and showed 7% failure after 500 cycles of TCT.

ITRI also reported on the reliability performance of two capillary underfills with different Tg and CTE used for µbump bonding on a silicon interposer.

The 20 um pitch µbumps were composed of 5um Cu / 3um Ni / 5um Sn2.5Ag (solder cap). Thermo-compression bonding was used to interconnect the µbumps at 280 C for 15 sec and the gaps then filled by one of the two underfills. Their properties are shown in the table below.

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Temp cycling data resulted in the Weibull plot shown below. The mean time to failure of underfill A (higher Tg) vs B was 20% higher.

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Ishihara Sangyo Kaisha (ISK)

ISK described the development of oxidation resistant Cu nanoparticles (50nm). Cu ink was prepared and printed (13um thick). Thermal treatment [ 200 C for 60 min under N2 + O2 followed by 250 C for 60 min under N2 + H2] This thermal sequence “burns” off the organics and sinters the particles to form a 0.2um copper film with 0.5um cm resistivity.

Osaka Univ

Osaka Univ reported that Cu to Cu joining can be accomplished using Cu nanoparticle paste (10-20nm particles in glycol protective solvent) They examined the shear strength of the joint vs thermal treatment atmosphere and temperature. The strongest bond (40 MPa) was achieved through 673 K bonding for 300 sec under 15MPa pressure with a N2/O2 atmosphere.

Tohoku Univ and Korea Institute of Industrial Tech

Tohoku Univ and Korea Institute of Industrial Tech studied the interfacial reaction between solder filled TSV and copper pillar bumps. Ti layer  (50 – 400nm thick) was used as barrier layer between solder and Cu pillar bump. Thermal aging for 500 hrs at 150 C was conducted and the interface examined. IMC thickness increased with aging time and as thickness of Ti increased the IMC thickness decreased.

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For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 153 IMAPS DPC part 3 Leti, Dow, STATSChipPAC

Wednesday, July 3rd, 2013

Finishing up our look at the 2013 IMAPS Device Packaging Conference

Leti

Leti examined the reliability of die to wafer bonding using copper/tin interconnects.  Above 232 C tin rapidly reacts with copper to produce higher melting point intermetallic compounds.

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They studied thermal cycling, TC (500x -40 to +125 C) and high temp storage, HTS (84 hrs at +125 C) for both underfilled and non underfilled Cu/Sn joints and found that TC has a more pronounced negative effect on yield and electrical performance than HTS.

After thermal cycling one finds increased growth of the Cu3Sn layer and cracks at the Cu/Cu3Sn interface. Underfilling has a positive impact on yield and electrical performance.

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Leti also addressed the thermal and mechanical challenges of 3DIC integration.

In terms of mechanical issues, everyone agrees that BOW is the problem. Potential solutions include:

- compensation layers on both sides to match stress.

- compliant interconnect

- increase interposer thickness

- control polymer encapsulation.

The following is an interesting plot that they use to make the point that a thicker substrate is better for mechanical stiffness. IFTLE thinks this is a bit of an over simplification since it depends on the modulus of the insulator layers and the encapsulation and their thicknesses. Certainly the general conclusion is correct.

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Dow Chemical

Dow Chemical and Fraunhoffer IZM presented new data on BCB based  temporary bonding adhesive. The process flow for temp bonding is shown below:

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Wafers can be bonded at 80 C with a bond time of ca. 1 min. and subsequent oven curing at 210 C for 1 hour. They find no alignment shift after curing. Wafers show no voiding or delamination after 1 hr at 325 C indicating excellent stability for all backside processing.

Mechanical debonding at room temp needs no irradiation or chemical treatments to release the thinned wafer. The mechanical debond is reported to be “residue free.”

If bumped first, one can coat twice to build up greater than 80um of BCB. Mechanical peel off reportedly does not delaminate any bumps. Subsequent cleaning is done with IPA.

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Dow has also developed a pre-applied underfill materials set. We were shown 25um thick film roll that was 330mm wide.

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Dow also gave an update on the new BCB XP 120201 a new low stress version of their positive tone, aqueous developable 6500 series. It has reported  cure temp less than 180 C and an elongation at break now greater than 25%.

STATSChipPAC (SCP)

SCP, one of the acknowledged leaders in fan out WLP announced the use of a new organic dielectric which results in more robust mechanical performance and now allows the packages to pass -55 to +125 thermal cycling. They have gotten 11 x 11mm 28nm die in 14x14mm substrates on 0.4mm pitch to pass reliability.

For the latest on 3DIC and advanced packaging, stay linked to IFTLE…