"For EMIB and such, guess that only 1-3 metal layers (global routing) need physical re-design...so seemingly..." - Ed Korczynski| Comment from: IFTLE 329 3D Integration Leaders - Europe;...
Subu Iyer of IBM addressed the evolution of high end memory + logic systems.
Die may be attached face to face or face to back which allows for multi die stacking. The stacking process is very sensitive to die warpage and the handling of thin die and controlling their warpage is reportedly one of the key challenges.
James Lu of RPI reported on a novel partition and assembly approach that combines both the electromagnetic (EM) and analytical simulations to accurately model and analyze several through-silicon-via (TSV) based 3D power delivery networks, which are composed of various stacked-chips,
Due to the very large CTE difference between In and Si vs Cu and Si, InAu Î¼-bumps induce a huge amount of tensile stress (> 300 MPa) in the stacked die even at bonding temperature as low as 200C
The variations in electrical behavior due to thinning for PMOS and NMOS of Poly Gate devices are less than 2%; for HKMG devices, the variations are less than 1.7%. The device characteristics are preserved after the thinning process.
They conclude that the impact of wafer thinning, stacking, and TSV proximity effects to Poly and HKMG CMOS devices are analyzed. Little to no degradation to device performance due to TSV manufacturing demonstrates successful integration of state-of-the-art CMOS technology. This work provides essential information for future 3DIC integration.
For those of you interested in the difference between future high performance memory and mobile memory, Sitaram Arkalgud of Sematech has put together a nice slide addressing the differences
Arif Rahman, co-chair of the program, gave a presentation on the status of Altera 2.5D FPGA program with TSMC. They will combine FPGAs with a variety of technologies enabled by a high-speed chip-to-chip interface. Altera’s 20nm product portfolio will include die stacking capabilities. They see TSV process capability in place at foundry, IDM and leading OSATs.
In the pre conference symposium Marinissen of IMEC gave an in depth look at the state of 3D stack testing .
Currently more than 12 companies and 10 Universities and Institutes are reportedly working on TSV related programs. A TSV consortium include foundries, packaging houses, material suppliers and institutes is examining interposer issues including:
ST Ericsson / CEA Leti
The Wioming program was first described by ST Ericsson at last years 3D ASIP conference [see IFTLE 86, "3D Headlines at the RTI 3D ASIP part deux"].
"When the bulbs are twisted into their signature spiral shape. That’s when you get into trouble, because [phosphor] is brittle, and it can’t take the curve," says materials science Professor Miriam Refailovich, who led the research. This has led reports by the NIH (national institute of health) to warn "â??¦ don’t use them in lamps that are close to your body" [link] (like end tables next to your favorite reading chair ? or your childs bedside lamp where they read at night?).
Ogunseitan added that "Although widely hailed as safer than compact fluorescent bulbs, which contain dangerous mercury, they [LEDs] weren’t properly tested for potential environmental health impacts before being marketed as the preferred alternative to inefficient incandescent bulbs, now being phased out under California law."
Lionel Cadix of Yole updated 3DIC and 2.5D Interposer market trends and technological evolutions. He showed the following TSV wafer forecast by market segment.
Riko Radojcic presented the following Qualcomm assessment of where things stand in 3DIC technology. This indicates that we are in the productization mode worrying about business models and yield ramps and not any technical issues.