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IFTLE 133 SEMI ISS 2013 Comments from Samsung, GF, Intel and others

Monday, January 28th, 2013
The 2013 SEMI Industry strategy symposium (ISS) was held at its usual time and place – Half Moon Bay CA in January.  Lets take a look at some of the inputs from this meeting of heavyweights in the industry.

Samsung Foundry

Samsung has been a foundry source now for seven years. Ana Hunter foundry VP for Samsung Semiconductor.  Looking at the continuation of Moores Law Hunter said "28nm could continue on Moores Law without to many issues, at 20 nm you start to see things slowing down, at 14 nm we’re introducing finfet and that will help a lot from transistor capability… Customers are very eager to get the 14nm finfet technology because of the transistor improvements especially low power… We do have shrink scheduled from 20 to 14nm but not on the same curve as Moores Law." She sees fabs for 20-14nm are in the $9-10B range.

In terms of 3D IC  Hunter commented that   "3D packaging is an area that we are focusing a lot on at Samsung… We are focusing on TSV and wide IO memory for the future… It [3D] has some issues today, but we think that having everything under one roof, we will be able to ring out any problems with the technology and then offer it more broadly outside… we have customers who are quite interested in this technology."

Mark LaPedus of Semiconductor Manufacturing and Design  discussed this further with Hunter and reported the following "At this week’s SEMI Industry Strategy Symposium (ISS), Samsung disclosed plans that it will offer 2.5D/3D foundry services. Like TSMC, Samsung will provide a turnkey solution, meaning it will offer the front- and back-end work for customers. "To start with, we will do it all in-house," said Ana Hunter, vice president of foundry services at Samsung Semiconductor. "If everything comes from the same company, it’s going to save cost (and ensure quality)." [link]


Keyvan Esfarjani Intel TMG VP reported on the evolution of flash memory. He concludes that non volatile memory is a “critical enabler for growth in servers, phones, tablets and ultrabooks”. He adds that solid state drives are growing in client and enterprise segments.

Changes in Production Capacity and the Marketplace

Dan Hutcheson of VLSI Research indicated that 5 total companies can be expected to go down to 10nm for a total development cost of $20B.

Andy Oberst, Sr VP at Qualcomm used data from IDC to point out that 4Q 2010 was the point where shipments of smartphones and tablets exceeded desktops and notebook PCs.
Bill McClean of IC Insights earlier in the week had released his 20012 foundry data showing that UMC had slipped two shots down to fourth and GlobalFoundries and Samsung had both climbed up a notch in the foundry rankings.

McClean reported that we are globally down to twenty five  300 mm fabs and face the potential of fewer than ten 450mm fabs in the future. Who says consolidation is not happening?

Ajit Manocha, CEO of GlobalFoundries reported that we now had 6+B mobile phones in place for a world population of 7B.

GF predicts that the leading edge will drive 60% of total foundry market by 2016 representing a market of $27.5 B.

Another consideration is how many 300 mm wafers will be required to supply high end smartphones a few short years from now in 2016. Gartner data shows that in fact this will consume the majority of 300 mm capacity.

For all the latest in 3D IC and advanced packaging stay linked to IFTLE….

IFTLE 132 2012 IEEE IEDM: IBM, RPI, Tohoku Univ and TSMC ; Wide IO Memory

Sunday, January 27th, 2013
Several papers at the  Dec 2012 IEEE IEDM meeting were of 3D interest.


Subu Iyer of IBM addressed the evolution of high end memory + logic systems.

With the wider utilization of multicore processors and the need for even larger amounts of  cache, Subu expects cache-processor stacks to proliferate. The figure below shows 3D integrated eDRAM die. The aspect ratio of the TSV in the thinned die is <10:1 .="" a="" across="" and="" appropriate="" are="" as="" at="" chip-to-chip="" chose="" contact="" dimension="" dimensional="" fat="" few="" for="" hierarchy="" higher="" ibm="" incongruity="" integrate="" interconnects="" levels="" microns="" minimize="" nm.="" o:p="" of="" reasons:="" respect="" several="" tens="" the="" to="" tsvs="" two="" upper="" wire="" with="">

Die may be attached face to face or face to back which  allows for multi die stacking. The stacking process is very sensitive to die warpage and the handling of thin die and controlling their warpage is reportedly one of the key challenges.

Fully Packaged, Fully Functional eDRAM on a Logic face-to-face Die Stack on Organic Laminate fabricated in IBMs 32nm process


James Lu of RPI reported on a novel partition and assembly approach that combines both the electromagnetic (EM) and analytical simulations to accurately model and analyze several through-silicon-via (TSV) based 3D power delivery networks, which are composed of various stacked-chips,

interposer, and package substrate.

Tohoku Univ

A serious potential reliability issue is the local deformation produced in the stacked LSI die with respect to the die thickness and the sub-surface structures formed after stress-relief methods. From electron backscatter diffraction (EBSD) analysis, more than one degree (>1°) of local misorientation is created in the stacked chip around μ-bump region. This induces a large tensile stress above the μ-bump region and relatively small compressive stress in the bump-space region, which leads to an enhancement in the n-MOSFET mobility in the μ-bump region and decrease in mobility at bump-space region.

Due to the very large CTE difference between In and Si vs Cu and Si, InAu μ-bumps induce a huge amount of tensile stress (> 300 MPa) in the stacked die even at bonding temperature as low as 200C

Even after 500 cycles of temperature cycles , a 20 μm dia Cu-TSV array on 40- μm pitch induces -570 MPa of compressive stress and a large variation in the induced stress values between different TSVs in the same array. For the LSI die/wafer thickness of anything less than 50 μm, the Young modulus and hardness of the thinned die no longer behaves like a bulk single crystal Si, which severely increases the reliability risks in the highly integrated 3D-LSIs.

In another Tohoku / ASET collaboration they studied “Characterization of Chip-level Hetero-Integration Technology for High-Speed, Highly Parallel 3D-Stacked Image Processing System”. A CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, were processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking.


TSMC reported on “Thinning, Stacking, and TSV Proximity Effects for Poly and High-K/Metal Gate CMOS Devices in an Advanced 3D Integration Process”. Poly and High-K/Metal Gate (HKMG) CMOS wafers were successfully thinned and stacked, showing little to no degradation in the process.

The variations in electrical behavior due to thinning for PMOS and NMOS of Poly Gate devices are less than 2%; for HKMG devices, the variations are less than 1.7%. The device characteristics are preserved after the thinning process.

The chip-on-wafer (CoW) stacking process is found to have little effect on device performance. The Id-Vd and Id-Vg characteristics for PMOS and NMOS are found to have little to no degradation in stacking process. The power and time delay trade-offs of ring oscillators show comparable performances before and after the stacking process .

The TSV induced mechanical stress can affect the device performance. Both the experiment and simulation results show that Î??Idsat of HKMG is smaller than Poly Gate in both p- and n-channel MOSFETs as shown below. For PMOS, the Î??Idsat of HKMG device is around 0.3 times when normalized to Poly Gate device; for NMOS, the ratio is about 0.4 – 0.5.


Î??Idsat for HKMG device is proportional to TSV diameter square, independent of TSV orientation, device polarity, and device distance from TSV.

They conclude that the impact of wafer thinning, stacking, and TSV proximity effects to Poly and HKMG CMOS devices are analyzed. Little to no degradation to device performance due to TSV manufacturing demonstrates successful integration of state-of-the-art CMOS technology. This work provides essential information for future 3DIC integration.

Wide IO Memory Applications

For those of you interested in the difference between future high performance memory and mobile memory, Sitaram Arkalgud of Sematech has put together a nice slide addressing the differences

For all the latest on 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦..

IFTLE 131 RTI 3D-ASIP part 4: FPGAs, Testing , Activity at GlobalFoundries and in Mainland China

Saturday, January 19th, 2013
Part 4, the last in our updates of the RTI 3D-ASIP conference.

Arif Rahman, co-chair of the program, gave a presentation on the status of Altera 2.5D FPGA program with TSMC. They will combine FPGAs with a variety of technologies enabled by a high-speed chip-to-chip interface. Altera’s 20nm product portfolio will include die stacking capabilities. They see TSV process capability in place at foundry, IDM and leading OSATs.

Altera sees silicon interposer technology requirements:
- 1-4K chip-to-chip interconnects (2-4X in future)
- Micro-bumps: 30-50 micron pitch
- Interposer: 2-3 Cu damascene layers, optional backside RDL, up to reticle size, option for integrated passive components Rahman has looked at alternatives to the silicon 2.5D interposer technology:
 High-density organic substrate ($$)
- advanced development            
- 10X interconnect pitch vs. silicon interposer
Glass interposers ($)
- In research phase No interposer ($-$$$)
- True 3D is expected to be more costly ($$$) and is currently not available&- Face-to-face stacking in wire-bond and flip-chip ($) is available
He concludes that Future stacking solutions will most likely consist of all of the above

In the pre conference symposium Marinissen of IMEC gave an in depth look at the state of 3D stack testing .

3D stacking requires consideration of many more test points than conventional 2D testing. The extent  of testing is a cost/benefit analysis which compares yield and the % of the bad product that the testing could have detected.
Most probers cannot handle thinned wafers on dicing frames. Marinissen reveals that TEL now offers automated handling and probing  of 300 mm wafers on dicing frames.
Marinissen also showed the results of IMEC consortium partner TSMCs testing of logic + memory structures.
Global Foundries
Dave McCann of Global Foundries (GF) discussed 2.5/3D technical challenges and progress.
McCann compared the “open supply chain” (favored by GF) to the “Internal foundry model” favored by TSMC concluding that GF preferred to “utilize experience in the industry where it best exists”..
GF points out that memory architecture the choices in customer solutions agreeing with Amkor that 2.5D will not be a focus of smartphones.
They have gathered the following electrical data post thinning which shows little impact on electrical function.
Also of interest is their list of critical metrology and inspect steps:
Chinese Academy of Sciences
Prof. Daquan Yu of the Chinese Academy of Sciences-Institute of Microelectronics gave a presentation on “The Development of TSV Technology in China”.

Currently more than 12 companies and 10 Universities and Institutes are reportedly working on TSV related programs. A TSV consortium include foundries, packaging houses, material suppliers and institutes is examining interposer issues including:

- electrical, thermal, mechanical and reliability design guideline and simulation
-  TSV interposer fabrication technology
-  Assembly and reliability of TSV interposer with thin chip and substrate
-  System testing methods
TSV manufacturing equipment such as  TSV etcher, PVD for high AR seed dep and cleaning chambers  have been developed by mainland Chinese companies and are ready or will be ready soon while some tools such as ECD are not ready yet and CMP, bond and debond are not yet available.
There are several local companies working on plating, cleaning, metal etching chemicals and CMP slurries . Xpeedic Technology was founded in 2010 to provide high performance EDA software and electronic design engineering services.
 For all the latest on 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦.

IFTLE 130 3D-ASIP part 3: Wioming, Leti Interposers , ASSID, Remaining Bond-Debond Issues and more on CFLs and LEDs

Sunday, January 13th, 2013
Part 3 in our look at the 2012 RTI 3D-ASIP.

ST Ericsson / CEA Leti
The Wioming program was first described by ST Ericsson at last years 3D ASIP conference [see IFTLE 86, "3D Headlines at the RTI 3D ASIP part deux"].

This year partner Denis Dutoit of CEA Leti shared more information. WIOMING (Wide IO Memory Interface Next Generation) program was launched by ST-Ericsson with the goal to enable increased graphics performance at reduced power levels for its smartphone applications.
Wioming is thought to be the first product designed using the JEDEC wide IO memory standard. Wide IO memory test is enabled through the following SoC test modes:
CEA Leti
Patrick Ludec of CEA Leti described their std interposer technology as follows:
Front side micro pillars are 10 micron in height, 25 micron in diameter with a 50 micron pitch. They are composed of a  Cu/Ni/Au stack for oxidation protection. There are 100K per interposer. Backside RDL consists of 10 micron L/S with organic passivation and 250 micron dia on 500 micron pitch Cu/Ni/Au pillars (total thickness 70 micron).
They see interposers evolving into "smart interposers" which can be used as RF platforms such as the pacemaker component shown below.
Leti is convinced that decreasing the TSV diameter can decrease cost by taking up less surface area of the device. They are now capable of 3 micron diameters TSV in 15 micron thick Si.
Fraunhoffer IZM ASSID
Juergen Wolf of Fraunhoffer IZM gave an update on Fraunhoffer IZM activities at the ASSID (All Silicon System Integration) in  Dresden. They showed the following evaluation of temporary bond/debond technologies:Suss MicroTec
Wilfried Bair of Suss MicroTec looked at the technical issues holding back the bond/debond process and concluded the following are the current specs for the process.
IFTLE comment on the recent Consumer Union LED Press release
After my recent Lester the Lightbulb rant [link] SST gave equal time to the green enery lobby by printing a blurb from the “consumers union” indicating that their LED bulb “ hanging over the sink in our lightbulb lab” had been on for “19,000 hrs non stop” and then as if to brag added “â??¦unlike other tested bulbs which are cycled on and off”[ link].
To the uneducated consumer this may sound great, but it is just another bogus statement by the green power front. The point they miss (intentionally? or just ignorantly?) is that power cycling is required to see failure. It is well known that bulbs fail during such power surges not while the bulbs are lit. We have discussed this in depth in our previous Lester articles .
CFLs and UV exposure
Also, as if our friends in the CFL lobby aren’t having enough issues with mercury contamination[link], we now find out that there are also issues with UV generation which could turn your barc-a-lounger into a tanning bed (OKâ??¦ a bit of an exaggeration). All fluorescent light bulbs emit UV rays when hit with an electric current. In their normal construction the UV is absorbed by a layer of phosphors, on the inside of the bulb . If that phosphor coating cracks, UV light escapes. According to the researchers at Stony Brook [link], defects are common in nearly all the bulbs they collected from retail stores.

"When the bulbs are twisted into their signature spiral shape. That’s when you get into trouble, because [phosphor] is brittle, and it can’t take the curve," says materials science Professor Miriam Refailovich, who led the research. This has led reports by the NIH (national institute of health) to warn "â??¦ don’t use them in lamps that are close to your body" [link] (like end tables next to your favorite reading chair ? or your childs bedside lamp where they read at night?).

and now …….LED Hazards from both MDs and the Environmentalists
Inside most white LED bulbs is a blue light source, which is converted to a full spectrum of colors by phosphors. Unlike CFLs, even if the phosphor coating is damaged, the blue light is in the visible spectrum, and poses no danger to human skin.  However there are reports that such blue light waves may be “â??¦especially toxic to those who are prone to macular problems due to genetics, nutrition, environment, health habits, and aging” [link].
German scientists have warned that the large proportion of blue light emitted by CFLs can lead to a diminished production of the hormone melatonin which can lead to a wide variety of diseases and conditions: sleeping disorders, cancer, cardiovascular disease, etc. [link].The environmentalists at Univ of California are also focusing in on LEDs after finding that they contain "..lead, arsenic and a dozen other potentially hazardous substances." Evidently the “reds” contain "..more than 8x the lead allowed under California law."
According to Professor Ogunseitan "â??¦there had been no previous studies on whether LEDs should be categorized as hazardous waste either at the federal or state levels" and he cautioned that "consumers, manufacturers and first responders to accident scenes to take care when handling the light bulbsâ??¦.When bulbs break at home, residents should sweep them up with a special broom while wearing gloves and a mask, and crews dispatched to clean up car crashes or broken traffic fixtures should don protective gear and handle the material as hazardous waste." [ IFTLE says hummmm]

Ogunseitan added that  "Although widely hailed as safer than compact fluorescent bulbs, which contain dangerous mercury, they [LEDs] weren’t properly tested for potential environmental health impacts before being marketed as the preferred alternative to inefficient incandescent bulbs, now being phased out under California law."

California Assembly Bill 1879, which would have required advance testing of replacement products, was originally scheduled to go into effect on Jan. 1 but was opposed by industry groups, according to the university [link].
For all the latest on 3DIC and advanced packaging stay linked to IFTLE…

IFTLE 129 RTI 3D ASIP part 2: Market Update; Qualcomm and Amkor Comments

Monday, January 7th, 2013
Part 2 in our look at the RTI ASIP Conference which occurred in Dec 2012.


Lionel Cadix of Yole updated 3DIC and 2.5D Interposer market trends and technological evolutions. He showed the following TSV wafer forecast by market segment.

As of 2011 the top 3 players in 3D TSV revenue were all CMOS image sensor fabricators. That is expected to change in the next two years as the memory suppliers come on line.
3D stacked DRAM and 3D Logic SOC applications are expected to be the biggest drivers for  volume adoption of 3DIC technology in the next five years.

Riko Radojcic presented the following Qualcomm assessment of where things stand in 3DIC technology. This indicates that we are in the productization mode worrying about business models and yield ramps and not any technical issues. 

In terms of design status he offered the following:
Paul Silvestri of Amkor shared their perspective on the readiness of 2.5/3D technology and manufacturing. Silvestri indicated that "3D memory delivery has been slowed down a bit" and that Amkor does not see interposers going into mobile phones simply because there is no room for them" (This is something Matt Nowak of Qualcomm has been saying for years).
Thinning and backside processing is pretty much ready to go with the only exception being bond/debond which still needs improvement.

- Fine Pitch Cu-Pillar technology is well established in high volume production
- Wafer thinning equipment and infrastructure is well established with excellent
   thickness variation control at 2 micron
- Backside silicon etch equipment and infrastructure is well established with excellent
   uniformity variation control at ca. 3%
- Backside passivation (SiN and TEOS) equipment and infrastructure are well
  established with excellent thickness variation control at ca. 2 micron
- Backside passivation polish equipment and infrastructure is well established with
   excellent thickness variation control at ca. 1 micron
- Backside bump Equipment and infrastructure is well established with high volume
  capability in industry
- Wafer support equipment and infrastructure is well established with high volume capability in industry but the process is still in need of improvement

Back End of Line Processing
Testing of the memory stack is required prior to committing memory to package stack. The memory stack in this construction is the largest cost item.
The preferred sequence in most instances is interposer to substrate and then chips/memory stack to interposer because it follows the standard OSAT processing flow. In nearly all cases the foundry inserts the TSV (TSV middle) but then the wafers are finished either at the foundry (TSMC preferred) or at the OSATS (GlobalFoundries & UMC preferred).
Amkor’s take on interposers is as follows:
Stacked Memory Sources
Silvestri indicates that there are only two primary memory sources today. KGM is received on tape and reel, stacked memory in wide I/O format typically 2 die stacks, but some 4 die stacks.
Amkor projects the following financial benefits from 3DIC.
For all the latest on 3DIC and advanced packaging stay linked to IFTLE….