IFTLE 104 IMAPS DPC Part 2; Over 50% of TI WB Converted to Copper
Tezzaron Process Technology
Bob Patti showed off two Centip3De, a 3-D IC stack using 128 ARM Cortex M3 cores and 256 Mbytes of stacked DRAM from the Univ of Michigan and the 3-D MAPS, a massively parallel processor using 64 custom cores stacked with a block 256 kilobytes of scratch pad memory from Ga Tech. For more details on these see IFTLE 93, "2.5/3D at the 2012 ISSCC".
(Click on any of the images below to enlarge them.)
Amkor Discusses 2.5/3DIC
Amkor’s Ron Huemoeller reported that 3D vertical stacking is:
- today focused on 28 nm CMOS and moving to 22 nm
- application processors are near exclusively moving to OSAT finished wafer process flows
- network, CPU and GPU driven
…….. mother boards reduced from 10 to 6 layers
…….. reduce chip mask layers
…….. smaller x, y dimensions
- focused on large package bodies (40 -90 mm , near retical sized Si)
- both foundry and OSAT wafer flow processes being used
- improves wafer yield
- reduces time to market
- reduces mask layer count at advanced process nodes
Concerning the interposer supply chain:
- glass can be delivered in large panel or wafer format. Several glass companies [Hoya, Corning, AGC] are investing in capability to support glass interposer technology. Glass faces challenges for CMP / damascene processing.
According to Amkor several foundry sources are interested in manufacturing Si interposers and a couple are already delivering fully functional wafers. Currently design rules "are aggressive" i.e. less than 2 um L/S and 5 um vias.
Amkor indicated that the predominant interposer designs are what IFTLE has been calling "fine featured" as follows:
When looking at TSV products expected to enter the market in the next few years, Huemoeller offered the following roadmap.
TI Promotes Cu WB