Research Triangle Institutes 3-D Architectures for Semiconductor Integration and Packaging Conference, or 3D ASIP (as it has become known) normally finishes off the “3D conference circuit” for the year and is a good gauge of how far things have progressed in the last 12 months. At the 7th 3D ASIP in Burlingame CA a few weeks ago, there were several announcements, statements and rumors having significant impact on the 2.5/3D community.
Much of the “buzz” at this years meeting certainly centered around the presentation by TSMCs Doug Yu a regular attendee of this meeting. Yu repeated the case he had made earlier at the Georgia Tech Interposer Conference [see IFTLE 80, “GIT @ GIT” ], for the pure foundry model for 2.5 and 3DIC,
stating that TSMC was readying full beginning to end interposer manufacturing. Yu told the audience of more than 200 that sharing the fabrication process with OSATS was not the preferred option for TSMC because “â??¦the risk for the customer is too high” and therefore TSMC would “ take full responsibility and accept full risk”. TSM is proposing that such one stop shopping ( at TSMC) will be simpler, cheaper and more reliable than using multiple sources (i.e. foundries, assembly houses and potentially other partners). Since the profit margin for packaging and assembly is currently substantially less than that for a foundry like TSMC manufacturing chips, cost sensitive customers appeared worried that packaging and assembly costs would increase substantially if turned over to foundries. Yu remained steadfast in his assessment that the required investments and the technology needed to handle thinned wafers would require that the foundries take control of such processing. “This is a new ballgame, the old ways of doing business are out of date for this new technology” Yu reiterated. Rumored to be currently working with only a handful of 2.5D/3D customers ( including Xilinx), Yu indicated that “â??¦new customers will have only the integrated solution proposalâ??¦..some, but not all of them [customers] want us to work with other partners, but many like our new approach very much".
Certainly with their customer Xilinx being first to enter the market with their 2.5D based Virtex 2000T FPGA, TSMC appears ahead of the rest of the foundries in this regard. Currently, TSMC is manufacturing the Xilinx chips and manufacturing and bumping the Xilinx interposer. Xilinx is using Amkor to assemble the FPGA chips on the interposer and the interposer onto a BGA package. Since the interposers are using 65 nm dual damascene processing for the multiple layers of RDL, in reality this is something that the assembly houses currently aren’t equipped to handle. More on that below.
When asked about the incorporation of other foundries chips onto the interposer or chip stack, Yu responded that there is no need to go to other foundries / IDMs except for memory, and that TSMC would partner with one or more memory suppliers to have that issue resolved.
Cho (Samsung) and Yu (TSMC) enjoying lunch at ASIP.
Is Samsung a potential 2.5/3D partner for TSMC ?
Microelectronic Consultants of NC
During my presentation detailing the status of 3DIC entering 2012, the issue of interposer categories came up. Basically interposers can be categorized as either being high density l/s ~ 1µm /1 µm which could only be manufactured by CMOS fabs/foundries and what we can call “coarse” featured interposers with l/s > 5 µm / 5 µm. The latter could be fabricated by ay of the OSATS who all have standard bumping and WLP processes capable of standard RDL. In a later presentation (IFTLE 86 next week) Raj Pendse of STATSChipPAC indicated that 5 um l/s and sub 25um TSV pitch was the transition point between OSAT and foundry capability
While all the OSATS have such capability, products have not yet been announced that would use such course dimensioned interposers and none of the OSATS have announced any intention to produce any interposers. One OSAT requesting anonymity later commented “It is correct that we are not offering “coarse” interposers , although we have capability to produce them – this is because we don’t see ourselves competing in that space with foundries and don’t think it will be a viable biz worth chasing and investing capital and resources in”. Eric Beyne, I MEC, during his presentation also questioned whether coarse interposers would provide enough value to be integrated into products. Similar responses were received from other OSATS in attendance.
Despite those comments, unsubstantiated rumors swirled at the conference that Siliconware had or was about to purchase a complete 2.5D/3D line from Applied Materials which included dual damascene capability so they could enter into manufacturing of high density interposers. Neither Applied nor Siliconware [SPIL] would confirm or deny the rumors, but it was interesting that SPIL customer, graphics chip maker NVIDIA in their presentation (see below) indicated that they would require 2.5D soon.
If the SPIL rumor is true, such a play might force other OSATS to follow suiteâ??¦.we shall see.
LeiLei Zhang, of NVIDIA, made what could become the rallying cry of the upcoming 3D decade when she said “Scaling is ending. Let’s get over it and move our resources elsewhere.” Zhang declared that for them bandwidth is the issue. She indicated that NVIDIA is likely to use a turnkey solution such as TSMC is offering with such 2.5D TSV solutions entering the NVIDIA roadmap with their TESLA and CUDA high end networking GPU product lines.
Although she wouldn’t indicate who her fabricator partner was, Zhang detailed the Nvidia Interposer program Status as follows:
- Demonstrated working process on very difficult test vehicles
- Reliability data looks OK but limited
- Long development cycle time
- Need more industry resources – both equipment and manpower
- Thin wafer Transport not Advised
- Assembly yield limited by Interposer warpage
- Non-wetting µbump
- Need Assembly Process, die thickness, µbump, materials optimization
- Biz model unclear
- Must choose between traditional supply chain & full turnkey solutions
Ivo Bolsens VP and CTO of Xilinx detailed their Virtex 2000T FPGA which he claims delivers 4X the compute performance as the current largest monolithic device. IFTLE has previously covered the performance of this device in detail. [ see IFTLE 73, “Xilinx shows 2.5DVirtex 7 at IMAPS 2011” ]
While Altera’s Bradley Howe predicted that “â??¦there are 8-10 years left to scaling, and then 3D will be the solution” he was quick to show 2.5D prototypes they are reading for the market, evidently a lot earlier than that. With arch rival Xilinx already sampling the market with 2.5D products that’s probably a good idea.
Seen at the RTI ASIP:
Next week we will finish up coverae of RTI ASIP. For all the latest in 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦