IFTLE 76: Advanced Packaging at IMAPS 2011, recent 3D announcements
PDMS stamps have found a lot of use recently as stamps for soft lithography. NuSil, maker of high purity silicones gave an interesting presentation on PDMS (polydimethylsiloxane). Evidently there are impurities in the PDMS that must be removed to produce a low outgassing product (required for space use), and fillers can be added to adjust its natural mechanical properties.
Specialty Coating Systems gave a presentation on their Parylene (xylylene polymers) CVD polymer product line which can be used as chemically inert barrier layers. Of special interest were the properties of Parylene HT which shows resistance toward thermal and or oxidative degredation up to 450°C and its UV resistance makes it a candidate for use as a protective layer for LED devices.
Daetec has looked at PBI (polybenzimidazole) as a temporary bonding material due to its properties of high thermal resistance, low outgassing and low stress.
Freescale reported on the adhesion of molding compound to SiN and SiON passivation surfaces. Both passivation surfaces were treated with O2/Ar plasma prior to the molding process. It is found that the SiN surface performed better than SiON electrically without showing any delamination for the mold compound studied. Both passivation surfaces were analyzed by TOF-SIMS immediately before and after the pre mold plasma treatment. The major observed difference was in OH group intensity. OH is increased on the SiN surface after plasma treatment while it is decreased on the SiON surface after treatment. It is inferred that the presence of OH group enhances the mold compound adhesion.
Kaist has studied the suppression of Kirkendall void formation in Sn/3.5Ag /Cu solder joints by pre-annealing. Pre annealing electroplated copper at 500-600°C for 2 hrs significantly suppresses Kirkendall void formation in the Sn-3.5Ag/Cu solder joints. Grain growth was observed as anneal time and temperature increased. SIMS analysis shows the annealed Copper films contained less C and S impurities.
Pac Tech has examined "Wafer level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30Î¼m " [PDF link]. They have examined placing solderballs by both WLSST (Wafer Level Solder Sphere Transfer) shown below and SB2 (solder sphere jetting)
For WLSST 40Î¼m solder balls were successfully placed while balls < 40Î¼m were not — because such placement requires a stencil with 15Î¼m openings and no stencil manufacturers can deliver such a stencil today.
Solder jetting with 30Î¼m SnAg3Cu0.5 solder balls was successful, although such small balls of other solder compositions were difficult to obtain from suppliers. Underfill processes for flip chips with 30Î¼m and 40Î¼m solderballs were developed. Reliability was tested according to MIL 883G — 8000 temp cycles between -55 and +125°C were passed.
Recent announcements in the 3D infrastructure
EV Group, IZM-ASSID JDA to develop chip-to-wafer temporary bonding
Upgrading 3D wafer level technologies to 300mm wafer size is the next step in effectively assisting leading companies in meeting the requirements of their future products. The ASSID (All Silicon System Integration Dresden), part of the Fraunhofer IZM Berlin, was established to meet this specific challenge. [see PFTLE 74: "All Silicon System Integration Dresden (ASSID) -- A 300mm 3D IC line for Germany"]
As part of this program, ASSID and EVG have announced an agreement to jointly develop high-volume temporary bonding and debonding processes to support chip-to-wafer bonding manufacturing processes for 3D IC integration applications. The joint-development project will take place in ASSID’s facility in Dresden. Process development work will be accomplished using EVG850 TB/DB systems already installed at Fraunhofer IZM-ASSID’s facility.
Brewer Science and EV Group come to agreement on ZoneBOND
The recent announcement by Brewer Science and EVG [see: Brewer Science, EVG commercialize temporary wafer bonding with zoning laws] means the IP issues between the two parties have been settled and the technology can move forward. ZoneBOND defines two distinctive zones on the carrier wafer surface with strong adhesion in the perimeter (edge zone) and minimal adhesion in the center zone. Therefore, only low separation force is required for carrier separation once the polymeric edge adhesive has been removed by solvent dissolution or other means. [see IFTLE 61: "Suss 3D Workshop at Semicon West"]
Numerous major players were intrigued by the technology but have been awaiting this resolution before they move forward.
In a linked announcement, EVG announced temporary bonding /debonding) equipment modules that support ZoneBOND technology [link]. It is interesting that EVG has opened its equipment platform to "enable the use of a wide range of adhesives from various suppliers to give customers the most flexible choice of bonding materials." This can be interpreted as meaning that they are no longer as closely wed to the Brewer product line as they once were, a position previously adopted by their competitor Suss Microtec.
Invensas aquires Allvia patent portfolio
Invensas, a wholly owned subsidiary of Tessera, has acquired the patent portfolio of Allvia and agreed to a two-year collaborative partnership to "further develop technology and IP in the 3D space".
The 64 patent portfolio consists mainly of technologies and processing dealing with "silicon interposers, TSV and micro bumping for wide IO mobile and 3DS DRAM."
While it certainly makes sense for Allvia to turn over the IP side of its business to Invensas and focus on foundry manufacturing for customers (including Invensas), it is certainly interesting that Invensas, whose stated corporate goals are to "acquire, develop and monetize strategic intellectual property" agreed to Allvia retaining a "back license" to offer the IP to other customers as was reported [link].
IFTLE interprets those comments as meaning they are offering the products, not licenses to the IP, but we may be wrong.
For all the latest in 3D IC and advanced packaging stay linked to IFTLE……….
Hope to see many of you at the RTI ASIP [ Architectures for Semiconductor Integration and Packaging] Dec 12-14!