IFTLE 64 Semicon 2011 TechXSpots on “beyond 40 nm” and “3D deep sub micron”
- between the 45nm and 8nm nodes, logic fab costs will double to $10 billion.
- only four companies will be able to follow Moore’s law by 2018
- the annual number of new fabs built will fall by 60% between 2011 and 2015
- by 2015 foundries will account for ~ 1/3 of the value of all semiconductors compared with ~ ¼ today
- by 2012, over 50% of packaging/test (SATS) will be outsourced
- by 2015 more than $30 billion in annual R and D expense will be saved by collaborative R and D.
Gartners estimation of total capacity availability by node and year is shown below followed by the fact that the finer feature chips are the ones driving packaging advances. Walker pointed out that between 1980 and 2010 the number of different packages available on the market has increased from 30 to more than 2200 !
Beyne pointed out that the M1 metal layers “above” the TSV consist of very narrow, high aspect ratio lines which require very flat surfaces: low dishing of Cu TSV CMP. The ULK dielectric layers in lower metal layers are of reduced strength which requires stable mechanical properties in the TSV i..e quire optimized post-plating annealing conditions to avoid copper protrusion.
To reduce the impact of TSV stress on devices, a keep-outzone is defined around the TSV structure. For advanced nodes, reducing this KOZ to a minimum becomes more important. The maximum stress induced in the Si by the TSV is in first order independent of the TSV diameter. The stress levels in the Si are proportional to (Ã??TSV/r)2 , with r the distance to TSV center, thus scaling down the diameter of the TSV by x reduces the “effective TSV area” (TSV+KOZ) by x4 ! [As we have noted mnany times in IFTLE, the smaller the TSV (diameter and AR), the better]