Part of the  

Solid State Technology


About  |  Contact

IFTLE 60 Semicon 2011: ASE, Alchimer, SPTS

Wu of ASE discusses Semiconductor Industry Status

At the recent Semicon West event in San Francisco, Tien Wu, COO of ASE, was the keynote speaker at the opening ceremony. Prior to joining ASE in 2000, Wu held several management positions within IBM.

According to Wu, the 53 years old semiconductor industry now accounts for 0.6 percent of worldwide GDP. He sees the semiconductor growth rate converging to ~ 7%. For the period 2011-2015 he is forecasting four years of stability with “mild growth” He sees this as a period of consolidation where only bold companies (“the bold ones”) will continue significant R&D and CAPEX spending. Wu described growth in the semiconductor industry over the past several decades as being driven by key applications. Aerospace in the 1970s, mainframe computers in the 1980s, PCs in the 1990s (global penetration now ~ 20%) cell phones in the 2000s (global penetration ~ 60%) and smart appliances in he 2010s . Wu noted that all of the applications are still running in huge volumes today.

Wu sees the industry polarizing into two factions ; (a) the infrastructure faction consisting of manufacturing heavyweights and (b) a systems faction [ IBM, HP, Apple] using software to interweave their product solutions and worrying about “branding “ their products. To quote Wu “The manufacturing heavyweights are driven by the systems power houses”

When comparing front end and back end operations Wu quoted figures showing that from 1980 to today $500B in CAPEX has been spent on the front end operations (avg of $26B/yr) whereas only $133B has been spent on the back end.

(ASE team joins COO Wu on stage after his Semicon Plenary lecture)

Alchimer Electrografting for MEMS, 3D and 2.5D Interposers
Steve Lerner, CEO of French startup Alchimer [see PFTLE 124; IFTLE 12] notes that progress is being made using their electro and chemi grafting products in the MEMS arena.  Earlier this year Alchimer  announced that the Microelectronics Innovation Collaborative Centre [C2MI (Quebec)]  had licensed Alchimer’s Wet Deposition process for MEMS 3D Research [link] to support the center’s 3D MEMS programs.
Luc Ouellet, VP of R&D at Teledyne DALSA Semiconductor (an earlier Alchimer licensee) reports that Alchimer’s electrografting technology “â??¦â??¦.provides strong support for work in advancing the technology for 3D MEMS manufacturing with a cost-effective approach”

Lerner also indicates that their new product family “AquiVantage” which provides metallization
for 3D Interposer and via last (backside) packaging is showing significant cost reduction for these applications.

AquiVantage uses the same basic technologies as the Alchimer’s wet processes for TSVs, reportedly providing concurrent wet deposition of TSV and front-side isolation, barrier, and copper fill/RDL, while eliminating CMP and dry deposition steps. It also supports smaller vias with higher aspect ratios. On the backside, the AquiVantage process allows selective maskless growth of the on-silicon isolation layer, eliminating an expose/develop/etch/clean lithography process cycle.


IFTLE sat down with Paul Linder, executive technology director and Markus Wimplinger director of EVGs business unit for technology development and intellectual property, to discuss their views on 3DIC commercialization and better understand their new temporary bonding metrology module which seeks to minimize the product at risk in a production environment.

Wimplinger noted that they have 1 customer already in production and that several are very close. Although they are wary to name names without customer approval , we have all seen their joint announcements with Amkor and their equipment installed at the joint programs of Leti / ST Micro and Fraunhofer Dresden and Global Foundries.

When asked to sum up their activity in the now retired EMC-3D consortium of which they were a co-founder, Linder indicated that the EMC-3D roadshows were helpful to show the industry that there is a supply chain for 3DIC and that the technology was doable. Linder reports that by the end, there was a clear consensus on a std process flow and all in all he views this as a very successful collaboration.

EVG has recently announced that they have joined the Ga Tech 3D Systems Packaging Research Center as a Manufacturing Infrastructure Member. Linder indicates that their mission is to develop “â??¦technologies that will make silicon and glass interposers with TSVs a truly affordable packaging solution." EVG’s temporary bonding and debonding, chip-to-wafer bonding and lithography technology and process know-how will be included in the PRC’s Silicon and Glass Interposer Industry Consortium research program.

EVGs new inline metrology module reportedly allows customers to implement in line process control for thin wafer processing. The in line metrology module can detect a variety of process irregularities and defects during temporary bonding and debonding including the TTV (total thickness variation) of the carrier wafer, adhesive layer, bond stack and thinned wafer; bow/warp of the boded stack and voids in the bond interface.

For all the latest in 3D IC and advanced packagign stay linked to IFTLE…………………

Comments are closed.

Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.