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Archive for June, 2011

IFTLE 55 ECTC Discussions on 3D Processing

Tuesday, June 21st, 2011
Before we get started in this weeks ECTC topic, I wanted to mention that old friend John Lau from ITRI pulled me aside at the ITRI booth to show me a functional example of the interposer test vehicle that we discussed in IFTLE 52 ("3D and Adv Pkging at ICEP 2011). ITRI had several 3D IC focused presentations at this years conference (see below).
3D integration continues to receive considerable attention due to its envisioned potential to alleviate or reduce performance limitations in continued CMOS scaling
Details on 3D Processing Issues
 Effect of Etch Rate on Scalloping During Bosch Etching – ITRI
ITRI discussed their Bosch Etching process in detail. In general, the higher the etch rates the larger the scallops; for 1μm-dia TSVs, the effect of etch rate on the scallop is very small and the scalloping ranges from 57 nm to 83 nm (etch rate 1.7μm/min – 2.13μm/min); for 10μm-dia TSVs, the scalloping ranges from 107 nm to 278 nm (etch rate 3.5μm/min – 5.8μm/min), for 20μm-dia TSVs, scalloping is sizable ranging from 93 nm to 225 nm (for etch rate 4.2μm/min – 8.8μm/min); for 30μm-dia TSVs scalloping is significant, ranging from 97 nm to 258 nm (etch rate 4.6μm/min – 9.5μm/min); and for 50μm dia TSVs scallop is large ranging from 99 nm to 235 nm (etch rate 5.2μm/min – 11μm/min).
ITRI lists the following issues to be considered for high quality etching:
Impact of Slurry in Cu CMP – ITRI
ITRI discusses the minimization of dishing during the removal of thick Cu plating overburden due to filling TSVs and backside isolation oxide CMP for TSV Cu exposure. In order to obtain a minimum Cu dishing on the TSV region, proper selection of Cu slurries and a  two-step Cu polishing process was developed. The bulk of Cu is removed with the slurry of high Cu removal rate and then the Cu surface is planarized with the slurry of high Cu passivation capability at the second step. The Cu dishing can be improved up to 97% for the 10μm-diameter TSVs on a 300 mm wafer. They reached the following conclusions:
1. For Cu slurry selections for the wafer front side Cu CMP for TSVs and RDLs, the slurries of high removal rate should go along with that of high passivation capability to reduce the metal dishing. Using the slurry with high Cu removal rate to remove the thick Cu overburden on the field and changing to the slurry with high Cu passivation capability to clean the remaining Cu tends to have a much less metal dishing.
2. The Cu plating performance affects the metal/oxide dishing/erosion after CMP. Minimizing metal recess or dimple right on the patterns after Cu plating is an important indicator for reducing dishing/erosion after CMP. For TSV plating, transferring from Cu recess to Cu protrusion will lead to a much smaller post-CMP metal dishing.
3. Wafer edge trimming procedure before temporary bonding and backside grinding reduces edge chipping for the subsequent processes. 0.5 mm edge trimming can eliminate the edge chipping issue for a thinned wafer.
4. For backside oxide CMP for TSV Cu exposure, low pressure  should be used to reduce edge chipping during processing.
Selection of Adhesive Materials for Temporary Bonding – ITRI
Most thin-wafer handling solutions are wafer-support-systems: the wafer to be thinned is temporarily bonded on a supporting wafer with an adhesive and thinned down to the required thickness to expose the through silicon vias TSVs. Thin-wafer handling systems can be classified by the five material solutions [Brewer Science(BSI), 3M, TOK, DuPont and Thin Materials (T-MAT),] available through equipment vendors such as EVG, Suss and TOK.
The different material vendors provide various temporary bonding and de-bonding methods which significantly influence the material selection, equipment in demand and choice of silicon vs glass carrier. De-bonding processes involve various release methods including : (a) mechanical (TMAT), (b) thermal (BSI), (c) solvent (BSI, TOK), and (d) laser (3M, DuPont). A transparent glass wafer is required to serve as the carrier for UV cure and laser release which costs more than a normal Si carrier.
ITRI has shared the following conclusions:
1. Wafer thinning and PECVD-SiO2 deposition are the most critical steps for backside processes in thin-wafer handling making it only necessary to qualify an adhesive for these two conditions.
2. Backside polymer isolation is suggested to replace the backside PECVD SiO2 step (where possible) to alleviate thin-wafer processing issues.
3. /span>No obvious change or de-lamination occurred in all the chemical resistance tests for the different adhesive options.
4. The TTV performance of composite wafers with thinner adhesive has been found to be much better than that with thicker adhesive (100μm. Good TTV control for thicker adhesive still has to be developed.
Wafer thinning and back side processing  - IMEC
 The temporary bonding approach followed by IMEC is based on Brewer Science WaferBond  HT-10.10. After the HT 10.10 layer shows an average thickness of 16.2μm and a thickness variation of about 1μm across a 300 mm wafer. The wafer is thinned down by back grinding to a thickness typically leaving 57μm Si remaining for a TSV depth of 50μm. The total thickness variation (TTV) of the thin wafer after grinding is in the range of 1.6μm across a 300 mm wafer.
After thinning, an isotropic dry recess etch process reveals the TSVs while keeping the Cu protected in the oxide liner. The presence of the oxide liner prevents Cu oxidation that could occur during subsequent steps of the process flow. Without any CMP step during nail reveal, the TSV depth variation of about 1μm across the device wafers is measured by high resolution profilometry.
After nail reveal, a thermally compatible low temperature nitride passivation layer is deposited below 200°C. This passivation layer prevents Cu diffusion through the thin wafer to the FEOL active layers when redistribution layers or microbumps are processed on the backside prior to stacking. A nitride layer was been selected over an oxide layer based on the barrier properties of the 2 materials.
Metrology and Inspection During Bonding and Thinning – IMEC
For the in-line monitoring of the 3D wafers in the bonding and thinning module IMEC has examined the SPARK platform from NandaTech which has both brightfield and darkfield inspection capabilities.
There are several key metrology and inspection (M and I) challenges that need to be solved for successful 3D stacking of dies. The most critical steps have been identified to be TSV depth control, glue layer defects and control of the grinding process.
In the TSV module the critical metrology needs are measurements of via depth during etch and also detection of voids after via fill. If there are any depth variations over the wafer it translates to TSV height variations and this can become important during the grinding procedure. This depth variation should be feed-forwarded to the grinder so that the grinding can stop at a safe distance from the TSVs.
During the bonding of the device wafer to the carrier, glue layer defects larger than a few microns become critical. If these glue layer defects are not detected pre-thinning they propagate to the device wafer. Therefore, it is equally important to have the right in-line metrology to detect defects after  bonding which would indicate the presence of glue layer defects.
 During grinding it is absolutely vital to the residual Si thickness above the TSVs so that the TSVs are not prematurely exposed. The basic idea is to use a certain wavelength which will only partially penetrate the Si layer (i.e. lambda= 650 to 750 nm penetrates 1.5μm to 3.5μm) and then scan the wafer. If there is a TSV buried deeper than 3.5μm it won’t be scattering light. A map of residual Si thickness above the TSV can be generated from the image.
A proper feed-forward and a feedback system is necessary between the TSV, Bonding  and Thinning modules to compensate for process  variations.
Wafer Level Molding for 3D Components – Samsung
Wafer molding is carried out in the chip-to-wafer process to ensure suitable levels of mechanical strength are reached. The key to wafer level mold processing is the reduction of warpage.
Samsung has studied material issues  optimized the wafer molding process to reduce warpage.  CTE mismatch between 50um thinned wafer and mold compounds is the primary challenge.  Test vehicles (bottom wafers, top chips) were fabricated on 300 mm wafers. A top chip of 8×8 mm2 size was designed and the bottom chip (including TSVs) was designed to a 12×12 mm2 size with 50um thickness. Before wafer molding, a supporting carrier was attached to the backside of the bottom wafer for wafer processing, backside via exposure and pad finishing. The top chips were then stacked on the wafer. After molding, the carrier wafer was detached and diced. The molded unit device’s warpage after dicing was measured by shadow moiré from room temperature to 240°C.
Molding material modulus, CTE, mold thickness and top chip thickness appear to be the parameters that drive the results. The size of the top chip was the dominant factor for warpage.  Warpage variation was mainly found at the overhang area where no top chip is present, which meant that the mold CTE mismatch was worse than inside the top chip area. Thus, a narrow overhang design is important for wafer molding.
Mold compound composition also had a strong influence on warpage as shown in the table below.
Conclusions include:
1.       Warpage decreased with increasing bottom chip thickness, and smaller chip size. This was directly related to the stresses encountered by the CTE mismatch between the mold material and silicon chip.
2.       Warpage decreased by decreasing the CTE and modulus of the mold material. Low modulus levels decreased the overall stiffness of the package, which is not desirable given that thin wafers need to be manufactured for the TSVs (usually manufactured to under 100μm depth). The minimum modulus values vary according to the packaging process and infrastructure, which is why careful selection of this value is required.
3.       Warpage levels can vary for the same mold material type depending on the filler content and resin type. By studying the effects of changing the filler content, it was found that decreasing this quantity improved warpage, as well as affecting the package reliability. The amount of shrinkage during curing of the resin also affected the stress levels in the mold material, and hence the warpage levels as well.
4.       Additional research is required to reduce warpage levels at room and high temperature to 40μm and achieve the required reliability levels. Package materials needs more investigation.
For all the latest on 3D IC and advanced packaging stay linked to IFTLE…..
We are trying the address the typo errors in this blog. Please be patient while we try to locate the cause of these errors ! 

IFTLE 54 2011 ECTC and Glass Interposers

Sunday, June 12th, 2011
Greater than 1000 attendees enjoyed the 2011 Electronic Component Technology Conference [ECTC] in Orlando FL. 342 of 641 submitted abstracts were selected by the program committee for presentation.

The technical focus continued to be on 3D integration which included  6 sessions and several dozen poster presentations. There were also a large number of submissions dealing with electromigration, the issues and reliability of fine pitch 3D micro joints, and numerous new advanced packaging proposals. We will begin by looking at TSMC and Ga Tech presentations on glass interposers and take a look at the other topics in the following weeks.

Glass Interposers

Glass is being examined as  a low cost alternative to the Si interposer. Compared to organic substrates ( ca 15 ppm), glass (3.2-9 ppm) has better CTE match to Si (2.3 ppm). Glass also exhibits excellent surface flatness, dimensional stability, high electrical resistivity and the availability in thin and large panels. The main challenges for glass interposers include:

- the ability to form ultrafine pitch TSV at high speed
- thermo-mechanical reliability of copper filled TSVs in glass
- thermal conductivity of glass (Si>glass>PWB)

Although the fracture strength of a defect-free glass is high, it decreases dramatically with any surface or bulk defects, which could be caused by processes such as etching, cutting, drilling, or metal deposition.

TSMC reported on test interposers which consisted of 100 um diameter TSV drilled in 360 um thick glass substrates on 200 – 500 um pitch. The test structures had 1,521 I/O in area array on a 40 x40 mm substrate.

They found that glass fracture strength decreases with decreasing TSV pitch. Higher via density leads to less cross section area and lower strength is observed. Data scatter is reportedly  due to structural defect s inherent in the glass after processing. They found that coating the glass on both sides with a “thin film material” (which appears to be PI) resulted in marginal improvements (10-20%) in glass fracture strength.
 ANSYS modeling was employed to simulate the material deformation for stress and strain analysis when the package is simulated under temperature excursion. A flip chip BGA with BT substrate was modeled for comparison purposes. Solder material, die thickness, glass size, glass thickness, via diameter, via pitch, PI coating thickness and CTE of glass were all examined as variables. When replacing the BT laminate with glass ( CTE of 8..3 ppm) the deformation of the package increases from 0.15 to 0.27 mm due to the larger CTE mismatch between substrate and PCB. Due to reduced CTE mismatch between die and glass, the maximum stress is reduced by approximately 38% when compared to the organic substrate. The most significant factor appears to be die thickness. Thick Si die introduce higher stress on glass substrate, owing to its increased rigidity which restricts the glass and/or die from deforming to relieve the stress. The CTE of the glass is also important since higher CTE glass induces higher stress to the die. They found that a medium CTE (ca. 8.3 ppm) glass is better for lower die stress.
The substrate serves as an interposer between low CTE Si die and high CTE PCB. Glass with higher CTE reduces BGA balls stress but is harmful to the Si die and vise versa. Overall, from the TSMC simulations, the medium CTE glass substrate at around 8.3 ppm is demonstrated as the optimal choice for the package structure. Some of the other factors, such as glass thickness, via diameter and PI thickness do not seem to play a significant role to affect the stress of the die, BGA ball or glass.
A Georgia Tech PRC consortium is also looking at glass as an interposer candidate . The glass substrates (either borosilicate [CTE = 3.8 ppm]or “high CTE” [8.5 ppm] glass) are 180 um thick with 15 um thick polymeric coatings on top and bottom similar to the TSMC construction. The 30 um TSV are either filled or conformal. Panel sizes are currently 150 mm.

The conformal TSV exhibited similar electrical performance as the filled TSV but are expected to show better thermo-mechanical reliability behavior. Stresses in the polymer layers are higher for thicker layers as expected.
Electrical properties of the glass interposer were extracted from measured and simulated data on ring resonators [dielectric constant ~ 4.8 and loss tangent ~ 0.002 up to 19.4 GHz. Low insertion loss of less than 0.15 dB at 9GHz was measured for the TPVs in the thin glass interposer.
For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edgeâ??¦

IFTLE 54 2011 ECTC and Glass Interposers

Sunday, June 12th, 2011
Greater than 1000 attendees enjoyed the 2011 Electronic Component Technology Conference [ECTC] in Orlando FL. 342 of 641 submitted abstracts were selected by the program committee for presentation.

The technical focus continued to be on 3D integration which included  6 sessions and several dozen poster presentations. There were also a large number of submissions dealing with electromigration, the issues and reliability of fine pitch 3D micro joints, and numerous new advanced packaging proposals. We will begin by looking at TSMC and Ga Tech presentations on glass interposers and take a look at the other topics in the following weeks.

Glass Interposers

Glass is being examined as  a low cost alternative to the Si interposer. Compared to organic substrates ( ca 15 ppm), glass (3.2-9 ppm) has better CTE match to Si (2.3 ppm). Glass also exhibits excellent surface flatness, dimensional stability, high electrical resistivity and the availability in thin and large panels. The main challenges for glass interposers include:

- the ability to form ultrafine pitch TSV at high speed
- thermo-mechanical reliability of copper filled TSVs in glass
- thermal conductivity of glass (Si>glass>PWB)

Although the fracture strength of a defect-free glass is high, it decreases dramatically with any surface or bulk defects, which could be caused by processes such as etching, cutting, drilling, or metal deposition.

TSMC reported on test interposers which consisted of 100 um diameter TSV drilled in 360 um thick glass substrates on 200 â???? 500 um pitch. The test structures had 1,521 I/O in area array on a 40 x40 mm substrate.

They found that glass fracture strength decreases with decreasing TSV pitch. Higher via density leads to less cross section area and lower strength is observed. Data scatter is reportedly  due to structural defect s inherent in the glass after processing. They found that coating the glass on both sides with a â????thin film materialâ???? (which appears to be PI) resulted in marginal improvements (10-20%) in glass fracture strength.
 ANSYS modeling was employed to simulate the material deformation for stress and strain analysis when the package is simulated under temperature excursion. A flip chip BGA with BT substrate was modeled for comparison purposes. Solder material, die thickness, glass size, glass thickness, via diameter, via pitch, PI coating thickness and CTE of glass were all examined as variables. When replacing the BT laminate with glass ( CTE of 8..3 ppm) the deformation of the package increases from 0.15 to 0.27 mm due to the larger CTE mismatch between substrate and PCB. Due to reduced CTE mismatch between die and glass, the maximum stress is reduced by approximately 38% when compared to the organic substrate. The most significant factor appears to be die thickness. Thick Si die introduce higher stress on glass substrate, owing to its increased rigidity which restricts the glass and/or die from deforming to relieve the stress. The CTE of the glass is also important since higher CTE glass induces higher stress to the die. They found that a medium CTE (ca. 8.3 ppm) glass is better for lower die stress.
The substrate serves as an interposer between low CTE Si die and high CTE PCB. Glass with higher CTE reduces BGA balls stress but is harmful to the Si die and vise versa. Overall, from the TSMC simulations, the medium CTE glass substrate at around 8.3 ppm is demonstrated as the optimal choice for the package structure. Some of the other factors, such as glass thickness, via diameter and PI thickness do not seem to play a significant role to affect the stress of the die, BGA ball or glass.
A Georgia Tech PRC consortium is also looking at glass as an interposer candidate . The glass substrates (either borosilicate [CTE = 3.8 ppm]or â????high CTEâ???? [8.5 ppm] glass) are 180 um thick with 15 um thick polymeric coatings on top and bottom similar to the TSMC construction. The 30 um TSV are either filled or conformal. Panel sizes are currently 150 mm.

The conformal TSV exhibited similar electrical performance as the filled TSV but are expected to show better thermo-mechanical reliability behavior. Stresses in the polymer layers are higher for thicker layers as expected.
Electrical properties of the glass interposer were extracted from measured and simulated data on ring resonators [dielectric constant ~ 4.8 and loss tangent ~ 0.002 up to 19.4 GHz. Low insertion loss of less than 0.15 dB at 9GHz was measured for the TPVs in the thin glass interposer.
For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edgeâ??¦

IFTLE 53 One Year Later?. Amkor / TI High Density Copper Pillar Bump Technology

Monday, June 6th, 2011
In late June 2010 Amkor and TI announced that they had qualified and begun production of the industry’s first fine pitch copper pillar flip chip packages – shrinking bump pitch up to 300 percent compared to then current solder bump flip chip technology [see IFTLE 23, “Xilinx 28 nm Multidie FPGA, Copper Pillar Advances at Amkor â??¦”]


Very little technical detail was released at that time, presumably because of the rumored exclusivity TI was given as part of the joint development program. Full technical details were to be withheld a year till the 2011 ECTC conference, which just occurred this past week. We’ll be covering the overall ECTC technical content over the next few weeks, but I first wanted to focus on the Amkor / TI paper “Next Generation Fine Pitch Cu Pillar Technology – Enabling next generation Silicon Nodes” since we have all been waiting a year for the details which were presented by Curtis Zwenger (Amkor) and Mark Gerber (TI).

Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being the primary drivers for mobile phone applications. Traditional solder or Cu Pillar interconnect pitches have been 150um to 200um for both low and high end flip chip applications. Today wafers are routinely bumped at 140 – 180 um pitch with 90 um solder balls in area array. Advanced silicon nodes create challenges to fine pitch (less than 100 um) flip chip interconnects and the corresponding substrate technology. Use of low-k dielectrics, thinner ICs, and package warpage are challenges.

Migrating from wire bond interconnects to area array flip chip requires a redistribution layer be added to the device to provide the required interconnection pattern. Fine pitch flip chip is compatible with existing in-line and staggered wire bond pad patterns, avoiding the cost for redistribution of the circuit on the die. Amkor claims that 80 percent of their internal studies on converting existing area array flip chip designs to fine pitch designs resulted in a lower cost substrate due to metal layer count reduction and/or body size reduction.

Fine Pitch Cu Pillar Test Vehicle
The qualification vehicle was a 559 bump chip on 50 um pitch and a 0.4 mm BGA array coming off the substrate ( 12 – 14 mm PoP body size).

Qualified design dimensions are shown in the figure below. Composition of the solder cap and the Pb free solder were not identified.

The primary process development challenge centered on the flip chip attach and bonding processes. For Cu Pillar flip chip with pitches less than 100um, the placement accuracy of the die to substrate is critical to help ensure a high yielding manufacturing process. Amkor found that thermal compression bonding was best suited for fine pitch copper pillar products. Thermal compression bonding, used in conjunction with a pre applied underfill (NCP = non conductive paste). The process flow is shown in the figure below.

It is important to control the height of the die in relation to the substrate. Pillar height, substrate capture pad height, and die thickness must be controlled to help ensure a stable process. For an over bonded Cu pillar die the solder cap can be squeezed out the sides of the joint causing solder shorts between the pillars.

The new fine pitch packages were put through standard JEDEC MSL L3 260 ºC un-biased package reliability tests including temperature and humidity, unbiased HAST, temperature cycle level B and high temperature storage tests as well as board-level reliability (BLR) testing (drop and temperature cycle) and biased component-level (CLR) reliability testing.


Rumors are that Amkor is adding additional fine pitch Cu Pillar capacity for TI and that the process is being transferred to TI who will be putting additional capacity in place for some of their own products. TI has indicated that they are open to licensing the fine pitch Cu pillar technology to others.


For all the latest on 3D IC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦..