IFTLE 35 3D Highlights at the RTI 3D ASIP Part 1
Lets first take a look at the Keynote presentations:
Subramanian Iyer, IBM
Confirming what PFTLE and IFTLE readers have been reading for several years now Iyer points out that :
- Scaling, strain engineering, and improved materials (eg. Hi K) will continue to improve performance , though at diminishing rates and certainly with diminishing returns
- A combination of voltage supply reduction, power budget constraints and design IP migration suggest that the days of dramatic raw performance gains are over
- Performance must come from elsewhere – Low latency memory integration provides significant system leverage
Iyer commented that he had spent the last 10 years of his life “..trying to get more memory closer to the processor”. Iyer indicated that integrating large amounts of low latency memory is one of the biggest challenges for modern multi-core processor design. Since modern processors contain 60-70% embedded memory, taking that memory off chip and using TSV to make such memory low latency and high bandwidth can in fact cut the size of the processor chip by as much as 50%. In addition placement of thin film deep trench decoupling caps can give a 5-10% performance improvement by stabilizing the power distribution.
Iyer labeled TSV as “..a necessary evil” which “..mess up logic or memory designs”. He adds that the TSV designs need to be done efficiently and adds that “..today we can do this with about a 5% penalty on the DRAM”
Iyer gave us indications for the first time that all vias middle are not equal. In fact he suggested that for some circuits intercepting at layer 4 might be the best circuit option. “..integration into oxide vs low K levels can be advantageous since they are much stronger and able to withstand the stresses that the TSVs generate on the structure” Iyer adds that one is “.. always trading off integration difficulty vs lower wirability capability due to blockage of the interconnect layers by the TSV.
Douglas Yu – TSMC
Dr. Yu, Sr Director of the Interconnect and Packaging Division, focused his presentation on the overall issues of packaging advanced node chips and how that relates to the future requirements for TSV and 3D stacking.
Yu indicates that with the rapid cost increases imposed by scaling TSMC sees chip scaling migrating into “system scaling” and 3D technology as being part of that whole movement.
Yu sees copper TSV and vias middle becoming the industry standards (as IFTLE has predicted for many years now) and he sees the copper protrusion issue as being solved [ see IFTLE 34 “3D IC at the 2010 IEDM” and “Cu protrusion, keep-out zones highlight 3D talks at IEDM” for details ]. They are currently comfortable with 50 um wafer thickness although they expect to go lower.
When asked about their commercial commitment to silicon interposers Yu responded “ Yes we will offer commercial silicon interposers as we have recently announced with our customer [Xilinx]" [ see IFTLE 23, “Xilinx 28 nm Multidie FPGAâ??¦”]
Yi-Shao Lai – ASE
Dr Lai filled in for Ho Ming Tong , who we were told was called away for an internal corporate meeting involving “a big investment for 3D IC”. Later in the day we heard from ASE that the budgeting was approved.
Lai indicated that ASE felt the industry was in much better shape for 3D IC then it was 3 years ago when ASE began looking at this technology in earnest.
Echoing the feeling of many participants Lai commented that the infrastructure could only be built by everyone “â??¦sharing critical information without leaking proprietary know how” Lai also requested further standardization of the supply chain. “ ..if chips will come from 3 or 4 foundries and the OSATS are chosen to do the backside processing and stacking, must the incoming materials be standardized so that OSATS can have a standard process for minimized cost? “
Anton Domic – Synopsys
Anton Domic, Sr VP and GM at Synopsys tried to give the EDA perspective on the migration from 2D to 3D. The theme for Synopsys, a late entrant into the 3D arena was that 3D was “heating up”.
Much is being made in other blogs about the comparison Domic made about 3D integration CoO. He indicated that 3D IC had a 5% impact on 300 mm wafer production and compared that to SOI (5%) and high k gates (10-20%). My feeling is that this was a generic statement and was made to indicate a relative comparison to things people all readily accept are happening.
We all understand that 3D is not a unit operation, it is an approach, and as such there is not one number to indicate its impact on cost. Cost modeling for 3D technology must be made on a system basis and as such there are NO numbers out there that I can say I believe yet. Now that real 3D IC technology (TSV, thinning, stacking) has been announced for memory [ see IFTLE 8, “3D Infrastructure Announcements and Rumors” ; IFTLE 27, “Era of 3D IC Has Arrived with Samsung Commercial Announcement” ] we will really begin to understand the true cost of implementing these technologies.
The same is true for and for 2.5D silicon interposers [ see IFTLE 23, “Xilinx 28 nm Multidie FPGAâ??¦”; IFTLE 27, “Era of 3D IC Has Arrived with Samsung Commercial Announcement” ]
Domic reiterated the point made by IBM’s Iyer – that TSVs are HUGE and added that TSV number and placement is crucial, mobility changes due to SPE (stress proximity effects) can be significant and thus keep out zones can be significant and that test is challenging.
When discussing silicon interposers which Domic labels “there already” because of the Xilinx announcement, Synopsys offers the following Implementation flow:
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