Part of the  

Solid State Technology


About  |  Contact

IFTLE 19 Semicon Taiwan 3D Forum Part 2

Continuing our look at the Semicon Taiwan 3D Technology Forum held a few weeks ago in Taipei.

In the past, SPIL has been rather silent about their plans for 3D IC. During his presentation at the 3D Forum, Carl Chen, VP of R and D, remarked that TSV solutions will be used short term for form factor driven reasons , mid term by performance and long term for cost considerations. This sequence is dramatically similar to the acceptance of wafer level packages (WLP) in the last decade.
SPILs roadmap shows single chip logic on interposer use in late 2010, memory stacking and logic and memory on interposer in 2011 and heterogeneous stacking post 2012. Chen commented that their 3D technology will “turn on in the very near future, depending on some technological breakthroughs and cost level”
Siliconware is calling their 2.5D interposer “TSI” for through silicon interposer. They offer the following chip-to-chip (interposer) and chip-to-wafer (interposer) sequences.

The current status of their copper pillar joining technology is shown in the figure below.


Nokia has been using MEMS microphones and camera modules both fabricated with TSV since 2006 and 2007 respectively.
Kauppi Kujala, Sr Tecnology Mgr at Nokia reports that memory stacking with TSV can offer miniaturization opportunities, performance improvements and power reduction.

Nokia currently sees wide I/O memory mating with logic devices as one of the main drivers for 3D IC adoption. Kujala proposes a single package with up to 4 DRAM for smart phone applications.
- 4-channel SDRAM x128 200MHz type interface, 12.8GByte/s
- Maximum memory die amount is 4 (1, 2 or 4)
- Wide IO interface grid / channel pitch of 50um
- TSV diameter of ca. 10um
- ca. 1200 uBump connection between chips

Kujala sees Interposers (2.5D) being driven by die /substrate pitch miss match and low  K mechanical fragility. Kujala, however warns that cost will be a major item in the adoption of interposers for 3D.
Nokia sees the need for standardization in areas like chip interfaces. Nokia is very supportive of JEDEC wide I/O standardization which reportedly will be ready in late 2011.

Yole Developpment

JC Eloy, CEO of Yole released their newest roadmap showing timing including initial qualification and first product on the market.


Fabless Qualcomm has been a strong proponent for 3D IC over the past few. At Semicon Taiwan 2010 Nick Yu, VP of Engineering indicated that Qualcomm would like to see 3D HVM with 3D IC by 2013.

Qualcom is also a strong proponent of standardization in order to accelerate adoption of the technology. Qualcomm is suggesting specific standards in the following areas and suggested which standards bodies (JEDEC, Sematech, Semi, IEEE, Si2, ANSI) should be involved.

- layout compatibility – data base compatibility
- modeling compatibility
- materials compatibility
- incoming spec
Process Flow
- handling spec

Qualcomm is looking for active industry professionals to contribute to these standards development programs and suggests the following venues:

3D design will be a focus area at the following 2010 events:
- Sematech 3D Stress Workshop : 19 Oct 2010, Dresden, Germany
- IEEE 3D-TEST Workshop: Nov 4, 2010, Austin, USA
- IEEE International 3D SIC Conference: 16 Nov, 2010, Munich, Germany
3D manufacturing will be a focus at the following 2010 events:
- IEEE International 3D SIC Conference: 16 Nov, 2010, Munich, Germany
- 7th RTI 3D ASIP Conf: 8 Dec, 2010, San Francisco, USA

For all the latest on 3D integration and advanced packaging stay linked to IFTLEâ??¦â??¦..

Comments are closed.

Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.