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IFTLE 11 3D In and Around the Moscone Part 2

â??¦â??¦â??¦.Continuing our look at the 3D related events at the recent Semicon West exhibition.


The ITRI Ad-STAC program has been discussed previously [ see PFTLE 105 “Taiwanese Focus on 3D IC”, 11/06/2009; PFTLE 99 “3D IC at ITRI”,09/24/2009. At the Suss “3D Bonding and Thin Wafer Handling “ workshop Yu-Hua Chen, Deputy Div Director, announced that there is now a team of 150 fully engaged in 3D design, build and test.

Per their previous announcements they still appear to be on time to have their 300 mm 3D line qualified by the 4Q 2010 as shown below.

Their roadmap now shows CPU + RAM stacking and memory stacking in the 2011 / 2012 timeframe, in sinc with other Pacific rim foundries and assembly houses.

Wilfried Bair at his Suss “3D Bonding and Thin Wafer Handling “ workshop detailed the process module options for their temporary bond / debond cluster tool as shown below. He announced that their bonding chambers were now stackable to allow for smaller fab footprint. A detailed look at the Suss options has been given earlier [ see PFTLE 82 “SUSS MicroTec Bonders for Temporary and Permanent 3D Bonding Solutions”6/24/ 2009 and PFTLE 96 “Suss Microtec Thin Wafer Processing 3D IC Workshop”, 9/5/2009]

The Suss equipment is compatible with Brewer (thermal slide), 3M (laser release), HD (laser release) and TMAT (mechanical release) bond/debond processes which use different mechanics to debond the wafer from the carrier. As a result, the modules for debonding must be configured to the specific process conditions required by the adhesive.

Bair indicated that they have major wafer and interposer programs underway with both IMEC and ITRI.
Alchimer fresh off a cash infusion by the Panasonic Ventures Group (link) held a workshop looking a 3D status in general and their “fully wet” 3D process in particular. We have discussed their process in detail [ see PFTLE 124 “Major Moves by Alchimer “, 3/21/2010 and refs therein]

Sang Sok Lee – CEO of Lenix (Korean materials and equipment supplier to Samsung, Hynix and LG) announced the commercial availability of modular process equipment for running the Alchimer "fully wet” electrografting via fill process. The fully automated system was exclusively designed for the electro- grafting and chemical-Grafting used in the Alchimer solution. Modules include: isolation, barrier, Cu seed, via filling ( capable to 5 micron Via Diameter) and annealing.

Alchimer CTO Claudio Truzzi described the latest advances in their “fully wet” TSV line and fill process focusing on their ability to do high aspect ration TSV and their low COO.
Alchimer CTO (l) Claudio Truzzi and CEO (r) Steve Lerner
Truzzi announced that their CoO modeling using the Yole cost model shows that the wafer cost for the EMC-3D process is ~$250 per wafer vs the ~ $165 that EMC3D has previously reported (shown below) and that $70MM is needed for the equipment for such a line. We can surely expect a response from EMC3D shortly!
Yole Developpement
Jerome Baron of Yole presented their latest forcast which I have shown below by application. Their prediction that memory on logic will begin to become the driving application by 2013 is certainly consistent with current Foundry and OSAT roadmaps.
Baron offers the following (5) challenges for 3D IC to become mainstream;
- Infrastructure availability and supply chain – : availability of a second source 3D packaging service provider is criticalâ??¦ Additionally, key strategic alliances / partnerships between memory suppliers, Logic IDMs, Foundries and Packaging subcontractors need to be in place for 3D SiP applications involving multiple-party ICs (memory, logic, interposerâ??¦)
- I/O standardization between interfaces such as memory / logic / interposer layers is critical. Such specifications need to be defined in order to establish a standardized and flexible supply chain (e.g. of JEDEC initiative for defining LPDDR3 memory standards for 3D TSV in mobile applications)
- Thermal management and interconnect reliability: in many applications such as stacking of DRAM modules, SSD for enterprise market and memory + logic stacking applications, thermal management is certainly the biggest barrier to entry for 3D if we cannot manage to dissipate heat well through the whole package.
- Shift in the Design / Test method paradigm and system co-design: heterogeneous functions, packaging, new CAD tools (thermal and mechanical simulation), test for KGD and new design architectures are required to get the full benefits of 3D.
- and finally Cost: depending on end-product, 3D TSV manufacturing cost should be reasonable and reduced in order to make it widely occurring in cost sensitive applications.
Coming soon:
- 3D at the Design Automation Conference (DAC)
- Semicon coverage of EVG, Sematech, Novellus, Verigy
- SEMATECH 3D coverage at Semicon 2010
- A look at the new ITRS roadmaps
- A GSA survey on 3D IC â??¦..and much more !
For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edgeâ??¦.

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