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IFTLE 10 3D IC at the 2010 IEEE IITC

Coverage of Semicon 2010 will continue next week. I’m interrupting that coverage to make sure we don’t forget to take a look at what occured at the IITC in June.

In 2008 PFTLE welcomed the IEEE IITC to the 3D IC bandwagon [ see PFTLE 37 “ IITC on the 3D Integration Bandwagon”,07/07/2008 ]. In each subsequent year they have continued to expand 3D IC coverage with quality papers as is shown below for their recent June 2010 meeting.


IMEC gave several interesting presentations at the IITC. One paper focused on the high temperature characterization of TSV capacitance, leakage and resistance. They conclude that although TSV capacitance marginally increases with the increase in temperature, TSV depletion behavior can still be exploited to reduce TSV capacitance at higher temperatures. TSV leakage measurements show that TSV oxide integrity is preserved even at higher temperatures (150C). The increase in TSV resistance matches estimations based on the positive temperature coefficient of Cu resistivity. The limited impact of temperature on measured power-delay characteristics of 2D / 3D ring oscillator circuits is due to the increase of TSV capacitance.

Another paper examined the impact of TSV – transistor proximity. Copper filled TSVs (see figure below), with a diameter of 5.2 μm and a length (height) of 22 μm, were designed and fabricated close to MOSFETs. The impact of a single TSV was examined on both PMOS and NMOS with a channel length of 0.13 μm to ~0.15 μm. For each transistor, a TSV was placed next to its active region. The distance between the edge of the channel and the TSV varied from 1.1 to 1.6 μm.

All the MOSFETs with TSVs in close proximity demonstrated normal functionality. Compared to the transistors without TSVs in proximity, no performance degradation of key transistor parameters was identified. These results show that at a minimum distance of 1.1 μm from MOSFETs, the current TSV structure has little impact on the device operation in this technology. Transistors surrounded by multiple TSVs also revealed no significant performance shift in comparison to the control cases with no TSV.

Thermal cycling between -55 and 125ºC was applied to the stacked dies. After 1000 cycles, all devices were functional and no degradation was observed with TSV proximity.

IMEC concludes that the ‘middle-TSV’ approach implemented on 130-nm CMOS technology platform has no significant impact on the electrical operation of MOSFETs and demonstrates good long-term reliability but wisely cautions that depending on technology and layout, this might not always be the case. Similar conclusions were reached previously [ see PFTLE 122, “3D IC at the IEEE ISSCC”, 03/12/2010 ]

IMEC has shared information about using a polymer TSV insulation previously [ see PFTLE 125, “3D IC at Fort McDowell”, 03/28/2010 ] In their most recent presentation they detail the processing for backside TSV of 50 and proposes two separate constructions for 50 and 100 µm thicknesses, (a) vs (b), as shown in the figure below.

For the 50 μm process the wafers are attached to a temporary carrier and thinned down to 50 μm. 5 μm wide ring-shaped trenches are patterned on the wafer backside and etched through the Si substrate to the BEOL pre-metal dielectric (PMD) stack. The trenches are then filled with a spin-on dielectric material. Low viscosity materials are better at void free filling of the insulation trenches.

For the 100 um process, a chamfered shape is used to avoid stress buildup at the Si corner. A sloped cavity is first etched then a second a vertical etch is done using a Bosch process IE process. Then a spin-on-dielectric from JSR is used to conformally coat the TSV. Polymer is then removed from the bottom of the hole by litho and dry etching. They indicate that this process is less likely to scale since it needs a big enough hole to do litho at the bottom of it.

Possible dimensions for these two TSV construction options are shown below.


Gu of Qualcomm shared possible integration challenges for high volume production. The interesting figure below shows the Si area in mm2 lost due to occupancy of TSVs as a function of aspect ratio for 100 um thick Si. They conclude that to maintain low Si area penalty ( i.e 2 mm2), the TSV aspect ratio should be approx 10 for 10,000 vias. This is true, but assumes the requirement of a 100 µm Si thickness.

As you may know as a reader of PFTLE [ see PFTLE 68, “Like Swallows Returning to San Juan Capistrano”, 03/20/2009 and PFTLE 44, “Upcoming 3D Integration events; Issues with the ITRS 3D Roadmaps”,09/11/2008], this author prefers a thinner Si (i.e. 30 um) which would lead to 1/3 the AR for the same lost area. Given all other things being equal lower AR always will equal lower cost.

More interesting to IFTLE are the comments Gu makes about plasma damage, namely “If the TSV is connected to a transistor during processing (which they are once the TSV are exposed from the backside – IFTLE), the plasma charge from wafer backside may damage the device gate oxide on wafer front side. Protection diodes are usually employed to protect transistor from plasma charge in the wafer front side. However, backside plasma light can be blocked from reaching the front side diode, which makes the protection diode less effective. Minimizing the plasma charge on backside process is important.” Certainly something to keep in mind.


Emma of IBM has been thinking about 3D IC and how to use them for a very long time. At IITC he gave a very interesting perspective on where we are in 3D IC integration and where we should be going.

Emma contends that in most commercial cases today, 3D is simply a packaging technique used to simplify integration. That its principle applications have been in high-volume markets where the costs of assembly are most important (such as cameras and cell phones); in markets where the physical size of the end-product is fixed (e.g., DIMMs); and in markets where both the power density and the inter-chip signal density are low. He contends that the goals of these applications are to make the end products simpler by integrating multiple components into a single stack, thereby enabling a single package and simplifying the subsequent assembly processes. It provides a way to continue the density scaling for a given footprint.


Modularity, Emma contends, can be one of the main advantages by providing a potentially simpler design flow. For example, large IP blocks (or even layers in disparate technologies from different vendors) can be incorporated into such a stack. This requires that there be well-defined interfaces, communication protocols, and technology ground-rules that will be common to all of the individual components (i.e. standardization) . He believes that the overheads associated with such well defined infrastructures, rules, and protocols are potentially lower than those required to compose the system using a traditional 2D approach.

This has the effect of “volumizing” those subsystems, which reduces their costs and their times-to-market. In addition, he proposes that 3D can allow clocking, power delivery and control, and test-related logic to be incorporated in a more modular way.


Scaling through-silicon-via (TSV) size and pitch in 3D enables high bandwidth and low latency interconnects among multiple device layers. This can enable massive internal bandwidth.

He also suggests we need to be considering system applications in which”… the logical elements of a system can be physically co-located in the {x,y} dimensions so that unprecedented bandwidth in the {z} dimension can allow the stack to do types of computation that would not be fathomable in 2-space”.

When taking a look at the constraints of 3D IC Emma offers that when combining differently constrained layers into a stack, 3D integration “…will tend to impose the combined constraints on each individual layer. Among those constraints are: (i) a shared power envelope (the amount of current drawn in any layer can impact the other layers when there are shared Power/GND TSVs), (ii) a shared thermal envelope for heat removal, and (iii) interactions between the layers in the form of noise (the reduced distances in the vertical direction, especially in thinned silicon will exacerbate noise issues). While not a major problem in low power systems, the first two constraints can be quite challenging for high-power and high power-density applications, like microprocessors”

He concludes “Today, the obvious uses for 3D are the ones in which the costs, power, interconnectivity, and profit margins are all fairly low. 3D offers some clear advantages in the future integration of systems: better volumetric density, lower raw power, smaller component count, and better modularity. But realizing these advantages requires solving a new set of problems in (literally) a new dimension.”

3D IC at the Upcoming IEEE CICC

Trying to keep you updated on what’s coming as well as what has transpired, I would be remiss if I didn’t mention the upcoming design activities at the IEEE CICC (Custom Integrated Circuits Conf) sponsored by the Solid State Circuits (SSC) and Electron Device (ED) societies.

3D veteran Rakesh Patel, who is now working on 3D IC with Global Foundries, informs IFTLE that CICC will be addressing 3D from a design perspective in their upcoming Sept 19-22 meeting in San Jose [link]

Their 3D forum will include:
- “3D Integration Infrastructure: Requirements to Support High Volume Production”, W. R. Bottoms, Third Millennium Test Solutions
- “3D IC – TSV Micro-bump Modeling and Design Implementation Tools”, Vassilios Gerousis, Cadence,
- “3D Packaging Evolution from an OSAT Perspective”, Raj Pendse, STATS ChipPAC
- “Challenges and Emerging Solutions for Testing TSV-Based Three-Dimensional Stacked ICs”, Erik Jan Marinissen, IMEC

In addition session 15 entitled “3D Design Considerations” will address the major 3D design topics of the day.

For all the latest on 3D IC and advanced packaging stay linked to Insights From the Leading Edge, IFTLE…………………

….Past issues of PFTLE can be accessed at……..

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